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Reel/Frame:	056713/0076			Pages:	7
		Recorded:	06/29/2021
Attorney Dkt #:	VARIOUS
Conveyance:	MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 78

Patent #:	6817007	Issue Dt:	11/09/2004	Application #:	10126911	Filing Dt:	04/19/2002
Publication #:	US20020186246	Pub Dt:	12/12/2002
Title:	INTERACTIVE LOOP CONFIGURATION IN A BEHAVIORAL SYNTHESIS TOOL

Patent #:	7302670	Issue Dt:	11/27/2007	Application #:	10313775	Filing Dt:	12/05/2002
Publication #:	US20040111692	Pub Dt:	06/10/2004
Title:	INTERACTIVE INTERFACE RESOURCE ALLOCATION IN A BEHAVIORAL SYNTHESIS TOOL

Patent #:	6829740	Issue Dt:	12/07/2004	Application #:	10354576	Filing Dt:	01/29/2003
Publication #:	US20030115521	Pub Dt:	06/19/2003
Title:	METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES

Patent #:	7478296	Issue Dt:	01/13/2009	Application #:	10354633	Filing Dt:	01/29/2003
Publication #:	US20030120988	Pub Dt:	06/26/2003
Title:	CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS TO A CIRCUIT-UNDER-TEST

Patent #:	7185308	Issue Dt:	02/27/2007	Application #:	10384013	Filing Dt:	03/07/2003
Publication #:	US20030154459	Pub Dt:	08/14/2003
Title:	CORRELATION OF BEHAVIORAL HDL SIGNALS

Patent #:	7093175	Issue Dt:	08/15/2006	Application #:	10736966	Filing Dt:	12/15/2003
Publication #:	US20040128599	Pub Dt:	07/01/2004
Title:	DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS

Patent #:	7308672	Issue Dt:	12/11/2007	Application #:	10753262	Filing Dt:	01/05/2004
Publication #:	US20040143801	Pub Dt:	07/22/2004
Title:	STRUCTURED ALGORITHMIC PROGRAMMING LANGUAGE APPROACH TO SYSTEM DESIGN

Patent #:	7516435	Issue Dt:	04/07/2009	Application #:	10870497	Filing Dt:	06/18/2004
Publication #:	US20050044518	Pub Dt:	02/24/2005
Title:	RESERVATION OF DESIGN ELEMENTS IN A PARALLEL PRINTED CIRCUIT BOARD DESIGN ENVIRONMENT

Patent #:	7293249	Issue Dt:	11/06/2007	Application #:	10888444	Filing Dt:	07/09/2004
Publication #:	US20050044513	Pub Dt:	02/24/2005
Title:	CONTRAST BASED RESOLUTION ENHANCEMENT FOR PHOTOLITHOGRAPHIC PROCESSING

Patent #:	7263641	Issue Dt:	08/28/2007	Application #:	10911033	Filing Dt:	08/03/2004
Publication #:	US20050015688	Pub Dt:	01/20/2005
Title:	PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY

Patent #:	7353468	Issue Dt:	04/01/2008	Application #:	10920988	Filing Dt:	08/17/2004
Publication #:	US20050071792	Pub Dt:	03/31/2005
Title:	SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION

Patent #:	7234094	Issue Dt:	06/19/2007	Application #:	10956988	Filing Dt:	09/30/2004
Publication #:	US20050081094	Pub Dt:	04/14/2005
Title:	AUTOMATON SYNCHRONIZATION DURING SYSTEM VERIFICATION

Patent #:	7539954	Issue Dt:	05/26/2009	Application #:	11061765	Filing Dt:	02/17/2005
Publication #:	US20050198598	Pub Dt:	09/08/2005
Title:	OPC SIMULATION MODEL USING SOCS DECOMPOSITION OF EDGE FRAGMENTS

Patent #:	7861207	Issue Dt:	12/28/2010	Application #:	11067504	Filing Dt:	02/25/2005
Publication #:	US20050278686	Pub Dt:	12/15/2005
Title:	FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES

Patent #:	7237221	Issue Dt:	06/26/2007	Application #:	11198971	Filing Dt:	08/08/2005
Publication #:	US20050278685	Pub Dt:	12/15/2005
Title:	MATRIX OPTICAL PROCESS CORRECTION

Patent #:	7509550	Issue Dt:	03/24/2009	Application #:	11213316	Filing Dt:	08/25/2005
Publication #:	US20060041812	Pub Dt:	02/23/2006
Title:	FAULT DIAGNOSIS OF COMPRESSED TEST RESPONSES

Patent #:	7987442	Issue Dt:	07/26/2011	Application #:	11221394	Filing Dt:	09/06/2005
Publication #:	US20060066338	Pub Dt:	03/30/2006
Title:	FAULT DICTIONARIES FOR INTEGRATED CIRCUIT YIELD AND QUALITY ANALYSIS METHODS AND SYSTEMS

Patent #:	7603641	Issue Dt:	10/13/2009	Application #:	11236222	Filing Dt:	09/26/2005
Publication #:	US20060080630	Pub Dt:	04/13/2006
Title:	POWER/GROUND WIRE ROUTING CORRECTION AND OPTIMIZATION

Patent #:	8037429	Issue Dt:	10/11/2011	Application #:	11241732	Filing Dt:	09/30/2005
Publication #:	US20060200790	Pub Dt:	09/07/2006
Title:	MODEL-BASED SRAF INSERTION

Patent #:	7729884	Issue Dt:	06/01/2010	Application #:	11267221	Filing Dt:	11/04/2005
Publication #:	US20060111873	Pub Dt:	05/25/2006
Title:	COMPACTOR INDEPENDENT DIRECT DIAGNOSIS OF TEST HARDWARE

Patent #:	7426668	Issue Dt:	09/16/2008	Application #:	11283499	Filing Dt:	11/18/2005
Publication #:	US20060146622	Pub Dt:	07/06/2006
Title:	PERFORMING MEMORY BUILT-IN-SELF-TEST (MBIST)

Patent #:	7426706	Issue Dt:	09/16/2008	Application #:	11359135	Filing Dt:	02/21/2006
Publication #:	US20060143586	Pub Dt:	06/29/2006
Title:	SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS

Patent #:	8161438	Issue Dt:	04/17/2012	Application #:	11435426	Filing Dt:	05/16/2006
Publication #:	US20060282492	Pub Dt:	12/14/2006
Title:	DETERMINING MUTUAL INDUCTANCE BETWEEN INTENTIONAL INDUCTORS

Patent #:	7191268	Issue Dt:	03/13/2007	Application #:	11495346	Filing Dt:	07/28/2006
Publication #:	US20060265531	Pub Dt:	11/23/2006
Title:	COMBINED HOST INTERFACE CONTROLLER FOR CONDUCTING COMMUNICATION BETWEEN A HOST SYSTEM AND MULTIPLE DEVICES IN MULTIPLE PROTOCOLS

Patent #:	7552416	Issue Dt:	06/23/2009	Application #:	11621082	Filing Dt:	01/08/2007
Publication #:	US20070198963	Pub Dt:	08/23/2007
Title:	CALCULATION SYSTEM FOR INVERSE MASKS

Patent #:	7689962	Issue Dt:	03/30/2010	Application #:	11704588	Filing Dt:	02/08/2007
Publication #:	US20070226659	Pub Dt:	09/27/2007
Title:	EXTRACTING HIGH FREQUENCY IMPEDANCE IN A CIRCUIT DESIGN USING AN ELECTRONIC DESIGN AUTOMATION TOOL

Patent #:	7454728	Issue Dt:	11/18/2008	Application #:	11759888	Filing Dt:	06/07/2007
Publication #:	US20070230645	Pub Dt:	10/04/2007
Title:	METASTABILITY INJECTOR FOR A CIRCUIT DESCRIPTION

Patent #:	7716622	Issue Dt:	05/11/2010	Application #:	11767385	Filing Dt:	06/22/2007
Publication #:	US20070245289	Pub Dt:	10/18/2007
Title:	MEMORY RE-IMPLEMENTATION FOR FIELD PROGRAMMABLE GATE ARRAYS

Patent #:	8122398	Issue Dt:	02/21/2012	Application #:	11811685	Filing Dt:	06/11/2007
Publication #:	US20070277144	Pub Dt:	11/29/2007
Title:	CONVERSION OF CIRCUIT DESCRIPTION TO AN ABSTRACT MODEL OF THE CIRCUIT

Patent #:	7755622	Issue Dt:	07/13/2010	Application #:	11818170	Filing Dt:	06/12/2007
Publication #:	US20070247456	Pub Dt:	10/25/2007
Title:	FLATTENING A THREE-DIMENSIONAL WIRE HARNESS REPRESENTATION TO TWO DIMENSIONS

Patent #:	7623220	Issue Dt:	11/24/2009	Application #:	11824558	Filing Dt:	06/28/2007
Publication #:	US20080174756	Pub Dt:	07/24/2008
Title:	SOURCE OPTIMIZATION FOR IMAGE FIDELITY AND THROUGHPUT

Patent #:	10643015	Issue Dt:	05/05/2020	Application #:	11869720	Filing Dt:	10/09/2007
Publication #:	US20080115097	Pub Dt:	05/15/2008
Title:	Properties In Electronic Design Automation

Patent #:	7890897	Issue Dt:	02/15/2011	Application #:	11939485	Filing Dt:	11/13/2007
Publication #:	US20080066032	Pub Dt:	03/13/2008
Title:	MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

Patent #:	7716614	Issue Dt:	05/11/2010	Application #:	12177018	Filing Dt:	07/21/2008
Publication #:	US20090007039	Pub Dt:	01/01/2009
Title:	HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS

Patent #:	7716548	Issue Dt:	05/11/2010	Application #:	12215593	Filing Dt:	06/27/2008
Publication #:	US20080294953	Pub Dt:	11/27/2008
Title:	REMOVING THE EFFECTS OF UNKNOWN TEST VALUES FROM COMPACTED TEST RESPONSES

Patent #:	8181129	Issue Dt:	05/15/2012	Application #:	12249320	Filing Dt:	10/10/2008
Publication #:	US20090044157	Pub Dt:	02/12/2009
Title:	ACYCLIC MODELING OF COMBINATIONAL LOOPS

Patent #:	7831871	Issue Dt:	11/09/2010	Application #:	12400664	Filing Dt:	03/09/2009
Publication #:	US20090172486	Pub Dt:	07/02/2009
Title:	TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT

Patent #:	8166360	Issue Dt:	04/24/2012	Application #:	12404553	Filing Dt:	03/16/2009
Publication #:	US20090177936	Pub Dt:	07/09/2009
Title:	DIRECT LOGIC DIAGNOSTICS WITH SIGNATURE-BASED FAULT DICTIONARIES

Patent #:	8201131	Issue Dt:	06/12/2012	Application #:	12404583	Filing Dt:	03/16/2009
Publication #:	US20090183128	Pub Dt:	07/16/2009
Title:	GENERATING TEST PATTERNS HAVING ENHANCED COVERAGE OF UNTARGETED DEFECTS

Patent #:	8311781	Issue Dt:	11/13/2012	Application #:	12480497	Filing Dt:	06/08/2009
Publication #:	US20090248388	Pub Dt:	10/01/2009
Title:	SELECTIVELY REDUCING THE NUMBER OF CELL EVALUATIONS IN A HARDWARE SIMULATION

Patent #:	7984354	Issue Dt:	07/19/2011	Application #:	12494121	Filing Dt:	06/29/2009
Publication #:	US20090327986	Pub Dt:	12/31/2009
Title:	GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS

Patent #:	8271928	Issue Dt:	09/18/2012	Application #:	12501716	Filing Dt:	07/13/2009
Publication #:	US20090276742	Pub Dt:	11/05/2009
Title:	AUTOMATING POWER DOMAINS IN ELECTRONIC DESIGN AUTOMATION

Patent #:	8438438	Issue Dt:	05/07/2013	Application #:	12948460	Filing Dt:	11/17/2010
Publication #:	US20110126064	Pub Dt:	05/26/2011
Title:	ENHANCED DIAGNOSIS WITH LIMITED FAILURE CYCLES

Patent #:	8806390	Issue Dt:	08/12/2014	Application #:	12972132	Filing Dt:	12/17/2010
Publication #:	US20110167394	Pub Dt:	07/07/2011
Title:	OPC CONFLICT IDENTIFICATION AND EDGE PRIORITY SYSTEM

Patent #:	8886509	Issue Dt:	11/11/2014	Application #:	13249037	Filing Dt:	09/29/2011
Publication #:	US20120022847	Pub Dt:	01/26/2012
Title:	COHERENT STATE AMONG MULTIPLE SIMULATION MODELS IN AN EDA SIMULATION ENVIRONMENT

Patent #:	8738352	Issue Dt:	05/27/2014	Application #:	13281790	Filing Dt:	10/26/2011
Publication #:	US20120136645	Pub Dt:	05/31/2012
Title:	Managing Communication Bandwidth in Co-Verification of Circuit Designs

Patent #:	8560906	Issue Dt:	10/15/2013	Application #:	13285899	Filing Dt:	10/31/2011
Publication #:	US20120174049	Pub Dt:	07/05/2012
Title:	TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Patent #:	9361424	Issue Dt:	06/07/2016	Application #:	14451091	Filing Dt:	08/04/2014
Publication #:	US20150067618	Pub Dt:	03/05/2015
Title:	INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS

Patent #:	10409937	Issue Dt:	09/10/2019	Application #:	15073980	Filing Dt:	03/18/2016
Publication #:	US20160267207	Pub Dt:	09/15/2016
Title:	MODELLING AND SIMULATION METHOD

Patent #:	10698702	Issue Dt:	06/30/2020	Application #:	15666355	Filing Dt:	08/01/2017
Title:	AUTOMATING INTERACTIONS WITH SOFTWARE USER INTERFACE

Patent #:	10571514	Issue Dt:	02/25/2020	Application #:	15792170	Filing Dt:	10/24/2017
Publication #:	US20190072606	Pub Dt:	03/07/2019
Title:	Single Simulation-Based Structure Function Mapping

Patent #:	NONE	Issue Dt:		Application #:	15873827	Filing Dt:	01/17/2018
Publication #:	US20190146847	Pub Dt:	05/16/2019
Title:	DYNAMIC DISTRIBUTED RESOURCE MANAGEMENT

Patent #:	10521547	Issue Dt:	12/31/2019	Application #:	15885142	Filing Dt:	01/31/2018
Publication #:	US20190121932	Pub Dt:	04/25/2019
Title:	COVERGROUP NETWORK ANALYSIS

Patent #:	10789409	Issue Dt:	09/29/2020	Application #:	15971216	Filing Dt:	05/04/2018
Publication #:	US20190303528	Pub Dt:	10/03/2019
Title:	PARASITIC EXTRACTION USING TOPOLOGICAL SHAPE DESCRIPTORS

Patent #:	10783303	Issue Dt:	09/22/2020	Application #:	16000888	Filing Dt:	06/06/2018
Publication #:	US20180349523	Pub Dt:	12/06/2018
Title:	THERMAL MODEL OBFUSCATION

Patent #:	NONE	Issue Dt:		Application #:	16105411	Filing Dt:	08/20/2018
Publication #:	US20190095563	Pub Dt:	03/28/2019
Title:	Printed Circuit Board Thermal Conductivity Determination

Patent #:	10546081	Issue Dt:	01/28/2020	Application #:	16134020	Filing Dt:	09/18/2018
Publication #:	US20190087522	Pub Dt:	03/21/2019
Title:	Full Memory Logical Erase For Circuit Verification

Patent #:	10716216	Issue Dt:	07/14/2020	Application #:	16157856	Filing Dt:	10/11/2018
Publication #:	US20190132955	Pub Dt:	05/02/2019
Title:	PIXELIZED THERMAL CONDUCTIVITY DETERMINATION FOR PRINTED CIRCUIT BOARDS

Patent #:	10592625	Issue Dt:	03/17/2020	Application #:	16171922	Filing Dt:	10/26/2018
Title:	Cell-Aware Root Cause Deconvolution For Defect Diagnosis And Yield Analysis

Patent #:	10579776	Issue Dt:	03/03/2020	Application #:	16174382	Filing Dt:	10/30/2018
Title:	SELECTIVE CONDITIONAL STALL FOR HARDWARE-BASED CIRCUIT DESIGN VERIFICATION

Patent #:	NONE	Issue Dt:		Application #:	16194839	Filing Dt:	11/19/2018
Publication #:	US20190155985	Pub Dt:	05/23/2019
Title:	COMMUNICATION PROTOCOLS DESIGN VERIFICATION THROUGH DATABASE SYSTEMS FOR HARDWARE-BASED EMULATION PLATFORMS

Patent #:	10732499	Issue Dt:	08/04/2020	Application #:	16195953	Filing Dt:	11/20/2018
Publication #:	US20190155143	Pub Dt:	05/23/2019
Title:	Method And System For Cross-Tile OPC Consistency

Patent #:	10775430	Issue Dt:	09/15/2020	Application #:	16224434	Filing Dt:	12/18/2018
Publication #:	US20190187207	Pub Dt:	06/20/2019
Title:	FAULT CAMPAIGN IN MIXED SIGNAL ENVIRONMENT

Patent #:	11681843	Issue Dt:	06/20/2023	Application #:	16248849	Filing Dt:	01/16/2019
Publication #:	US20190220745	Pub Dt:	07/18/2019
Title:	Input Data Compression For Machine Learning-Based Chain Diagnosis

Patent #:	11361248	Issue Dt:	06/14/2022	Application #:	16248866	Filing Dt:	01/16/2019
Publication #:	US20190220776	Pub Dt:	07/18/2019
Title:	Multi-Stage Machine Learning-Based Chain Diagnosis

Patent #:	10796047	Issue Dt:	10/06/2020	Application #:	16254324	Filing Dt:	01/22/2019
Publication #:	US20190228125	Pub Dt:	07/25/2019
Title:	FUNCTIONAL SAFETY SYNTHESIS

Patent #:	10691869	Issue Dt:	06/23/2020	Application #:	16256518	Filing Dt:	01/24/2019
Publication #:	US20190266311	Pub Dt:	08/29/2019
Title:	PATTERN-BASED OPTICAL PROXIMITY CORRECTION

Patent #:	11422188	Issue Dt:	08/23/2022	Application #:	16360223	Filing Dt:	03/21/2019
Publication #:	US20190293717	Pub Dt:	09/26/2019
Title:	Isometric Control Data Generation For Test Compression

Patent #:	10830815	Issue Dt:	11/10/2020	Application #:	16360691	Filing Dt:	03/21/2019
Publication #:	US20190293713	Pub Dt:	09/26/2019
Title:	Signal Probability-Based Test Cube Reordering And Merging

Patent #:	NONE	Issue Dt:	06/04/2024	Application #:	16361915	Filing Dt:	03/22/2019
Publication #:	US20200302321	Pub Dt:	09/24/2020
Title:	MACHINE LEARNING-BASED ADJUSTMENTS IN VOLUME DIAGNOSIS PROCEDURES FOR DETERMINATION OF ROOT CAUSE DISTRIBUTIONS

Patent #:	NONE	Issue Dt:		Application #:	16376315	Filing Dt:	04/05/2019
Publication #:	US20190311290	Pub Dt:	10/10/2019
Title:	Deep Learning Based Test Compression Analyzer

Patent #:	10769340	Issue Dt:	09/08/2020	Application #:	16411209	Filing Dt:	05/14/2019
Publication #:	US20190354654	Pub Dt:	11/21/2019
Title:	Automatic Moving Of Probe Locations For Parasitic Extraction

Patent #:	10895864	Issue Dt:	01/19/2021	Application #:	16413686	Filing Dt:	05/16/2019
Publication #:	US20190361425	Pub Dt:	11/28/2019
Title:	FABRIC-INDEPENDENT MULTI-PATTERNING

Patent #:	10796045	Issue Dt:	10/06/2020	Application #:	16432396	Filing Dt:	06/05/2019
Publication #:	US20190377839	Pub Dt:	12/12/2019
Title:	EFFICIENT BI-DIRECTIONAL PROPERTY-BASED PATH TRACING

Patent #:	10796070	Issue Dt:	10/06/2020	Application #:	16515451	Filing Dt:	07/18/2019
Publication #:	US20200026820	Pub Dt:	01/23/2020
Title:	Layout Pattern Similarity Determination Based On Binary Turning Function Signatures

Patent #:	10796046	Issue Dt:	10/06/2020	Application #:	16549929	Filing Dt:	08/23/2019
Publication #:	US20200233931	Pub Dt:	07/23/2020
Title:	MACHINE LEARNING-BASED PARASITIC EXTRACTION AUTOMATION FOR CIRCUIT DESIGN AND VERIFICATION

Patent #:	11025754	Issue Dt:	06/01/2021	Application #:	16738772	Filing Dt:	01/09/2020
Publication #:	US20210120106	Pub Dt:	04/22/2021
Title:	SYSTEM FOR PROCESSING MESSAGES OF DATA STREAM

Patent #:	10963612	Issue Dt:	03/30/2021	Application #:	16845139	Filing Dt:	04/10/2020
Publication #:	US20200327268	Pub Dt:	10/15/2020
Title:	Scan Cell Architecture For Improving Test Coverage And Reducing Test Application Time

Assignor

MENTOR GRAPHICS CORPORATION

Exec Dt:

12/30/2020

Newly Merged Entity Data

SIEMENS INDUSTRY SOFTWARE INC.

Exec Dt:

12/30/2020

Newly Merged Entity's New Name

SIEMENS INDUSTRY SOFTWARE INC.

5800 GRANITE PARKWAY, SUITE 600

PLANO, TEXAS 75024

Correspondence name and address
	SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
	3850 QUADRANGLE BOULEVARD
	ORLANDO, FL 32817

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