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Reel/Frame:026044/0090   Pages: 7
Recorded: 03/29/2011
Attorney Dkt #:92387.768766
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 26
1
Patent #:
Issue Dt:
06/13/2006
Application #:
10210858
Filing Dt:
07/31/2002
Title:
INPUT/OUTPUT CELLS FOR A DOUBLE DATA RATE (DDR) MEMORY CONTROLLER
2
Patent #:
Issue Dt:
12/16/2003
Application #:
10211691
Filing Dt:
07/31/2002
Title:
PROGRAMMABLE DELAY COMPENSATION CIRCUIT
3
Patent #:
Issue Dt:
08/29/2006
Application #:
10663327
Filing Dt:
09/16/2003
Publication #:
Pub Dt:
03/17/2005
Title:
PORT INDEPENDENT DATA TRANSACTION INTERFACE FOR MULTI-PORT DEVICES
4
Patent #:
Issue Dt:
05/30/2006
Application #:
10663328
Filing Dt:
09/16/2003
Publication #:
Pub Dt:
03/17/2005
Title:
METHOD AND APPARATUS FOR MULTI-PORT MEMORY CONTROLLER
5
Patent #:
Issue Dt:
11/20/2007
Application #:
10702916
Filing Dt:
11/05/2003
Publication #:
Pub Dt:
05/05/2005
Title:
REACTIVE PLACEMENT CONTROLLER FOR INTERFACING WITH BANKED MEMORY STORAGE
6
Patent #:
Issue Dt:
02/08/2011
Application #:
11752141
Filing Dt:
05/22/2007
Publication #:
Pub Dt:
11/27/2008
Title:
SYSTEM AND METHOD FOR BUILDING CONFIGURABLE DESIGNS WITH HARDWARE DESCRIPTION AND VERIFICATION LANGUAGES
7
Patent #:
Issue Dt:
12/25/2012
Application #:
11778433
Filing Dt:
07/16/2007
Publication #:
Pub Dt:
01/22/2009
Title:
SYSTEM AND METHOD FOR PROVIDING DATA INTEGRITY IN A NON-VOLATILE MEMORY SYSTEM
8
Patent #:
NONE
Issue Dt:
Application #:
11840217
Filing Dt:
08/17/2007
Publication #:
Pub Dt:
02/19/2009
Title:
EXECUTE-IN-PLACE IMPLEMENTATION FOR A NAND DEVICE
9
Patent #:
Issue Dt:
05/10/2011
Application #:
11856063
Filing Dt:
09/17/2007
Publication #:
Pub Dt:
03/19/2009
Title:
PROGRAMMABLE SEQUENCE GENERATOR FOR A FLASH MEMORY CONTROLLER
10
Patent #:
Issue Dt:
08/11/2009
Application #:
11869692
Filing Dt:
10/09/2007
Publication #:
Pub Dt:
04/17/2008
Title:
REACTIVE PLACEMENT CONTROLLER FOR INTERFACING WITH BANKED MEMORY STORAGE
11
Patent #:
NONE
Issue Dt:
Application #:
11934790
Filing Dt:
11/05/2007
Publication #:
Pub Dt:
05/07/2009
Title:
CONFIGURABLE AND REUSABLE NAND SYSTEM
12
Patent #:
Issue Dt:
01/25/2011
Application #:
11938725
Filing Dt:
11/12/2007
Publication #:
Pub Dt:
05/14/2009
Title:
SYSTEM AND METHOD FOR WEAR LEVELING UTILIZING A RELATIVE WEAR COUNTER
13
Patent #:
Issue Dt:
09/18/2012
Application #:
12022134
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
SYSTEM AND METHOD FOR PROVIDING COPYBACK DATA INTEGRITY IN A NON-VOLATILE MEMORY SYSTEM
14
Patent #:
Issue Dt:
05/17/2011
Application #:
12022138
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
METHOD AND APPARATUS FOR MEMORY MANAGEMENT IN A NON-VOLATILE MEMORY SYSTEM USING A BLOCK TABLE
15
Patent #:
Issue Dt:
05/03/2011
Application #:
12022146
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
READ DISTURBANCE MANAGEMENT IN A NON-VOLATILE MEMORY SYSTEM
16
Patent #:
Issue Dt:
10/09/2012
Application #:
12040782
Filing Dt:
02/29/2008
Publication #:
Pub Dt:
09/03/2009
Title:
METHOD AND APPARATUS FOR HIGH SPEED CACHE FLUSHING IN A NON-VOLATILE MEMORY
17
Patent #:
Issue Dt:
12/02/2014
Application #:
12054391
Filing Dt:
03/25/2008
Title:
OPERATION BASED POLLING IN A MEMORY SYSTEM
18
Patent #:
Issue Dt:
01/07/2014
Application #:
12143274
Filing Dt:
06/20/2008
Publication #:
Pub Dt:
12/24/2009
Title:
METHOD AND APPARATUS FOR DYNAMICALLY CONFIGURABLE MULTI LEVEL ERROR CORRECTION
19
Patent #:
Issue Dt:
06/12/2012
Application #:
12170237
Filing Dt:
07/09/2008
Publication #:
Pub Dt:
01/14/2010
Title:
METHOD AND APPARATUS FOR PARALLEL ECC ERROR LOCATION
20
Patent #:
Issue Dt:
04/26/2011
Application #:
12201937
Filing Dt:
08/29/2008
Publication #:
Pub Dt:
03/04/2010
Title:
SYSTEM AND METHOD FOR MANAGING NON-VOLATILE MEMORY BASED ON HEALTH
21
Patent #:
Issue Dt:
05/07/2013
Application #:
12248690
Filing Dt:
10/09/2008
Publication #:
Pub Dt:
04/15/2010
Title:
METHOD AND APPARATUS FOR IMPROVING SMALL WRITE PERFORMANCE IN A NON-VOLATILE MEMORY
22
Patent #:
Issue Dt:
05/26/2015
Application #:
12413928
Filing Dt:
03/30/2009
Publication #:
Pub Dt:
09/30/2010
Title:
DOUBLE DATA RATE MEMORY PHYSICAL INTERFACE HIGH SPEED TESTING USING SELF CHECKING LOOPBACK
23
Patent #:
Issue Dt:
01/17/2012
Application #:
12413998
Filing Dt:
03/30/2009
Publication #:
Pub Dt:
09/30/2010
Title:
METHOD AND APPARATUS FOR GATE TRAINING IN MEMORY INTERFACES
24
Patent #:
Issue Dt:
05/31/2011
Application #:
12414044
Filing Dt:
03/30/2009
Publication #:
Pub Dt:
09/30/2010
Title:
METHOD AND APPARATUS FOR DETERMINING WRITE LEVELING DELAY FOR MEMORY INTERFACES
25
Patent #:
Issue Dt:
04/23/2013
Application #:
12435550
Filing Dt:
05/05/2009
Publication #:
Pub Dt:
11/11/2010
Title:
METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN ASYNCHRONOUS CLOCK DOMAINS
26
Patent #:
Issue Dt:
01/17/2012
Application #:
12534004
Filing Dt:
07/31/2009
Publication #:
Pub Dt:
11/26/2009
Title:
REACTIVE PLACEMENT CONTROLLER FOR INTERFACING WITH BANKED MEMORY STORAGE
Assignor
1
Exec Dt:
03/28/2011
Assignee
1
2655 SEELY AVENUE
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
KILPATRICK TOWNSEND & STOCKTON LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO, CA 94111

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