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Reel/Frame:053476/0094   Pages: 27
Recorded: 06/17/2020
Attorney Dkt #:2515.5050
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 99
1
Patent #:
NONE
Issue Dt:
Application #:
10908254
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/03/2005
Title:
INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR
2
Patent #:
NONE
Issue Dt:
Application #:
10934835
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
03/02/2006
Title:
Wire sweep resistant semiconductor package and manufacturing method thereof
3
Patent #:
NONE
Issue Dt:
Application #:
11035637
Filing Dt:
01/14/2005
Publication #:
Pub Dt:
07/20/2006
Title:
Under bump metallurgy in integrated circuits
4
Patent #:
NONE
Issue Dt:
Application #:
11162828
Filing Dt:
09/24/2005
Publication #:
Pub Dt:
05/18/2006
Title:
HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
5
Patent #:
NONE
Issue Dt:
Application #:
11162971
Filing Dt:
09/29/2005
Publication #:
Pub Dt:
03/29/2007
Title:
SUBSTRATE INDEXING SYSTEM
6
Patent #:
NONE
Issue Dt:
Application #:
11163313
Filing Dt:
10/13/2005
Publication #:
Pub Dt:
04/19/2007
Title:
STACKED DIE PACKAGING SYSTEM
7
Patent #:
NONE
Issue Dt:
Application #:
11163547
Filing Dt:
10/21/2005
Publication #:
Pub Dt:
04/26/2007
Title:
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
8
Patent #:
NONE
Issue Dt:
Application #:
11163556
Filing Dt:
10/22/2005
Publication #:
Pub Dt:
08/10/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED INTERLOCKING LEADFRAME
9
Patent #:
Issue Dt:
12/01/2009
Application #:
11164329
Filing Dt:
11/18/2005
Publication #:
Pub Dt:
03/16/2006
Title:
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
10
Patent #:
NONE
Issue Dt:
Application #:
11276947
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
11
Patent #:
NONE
Issue Dt:
Application #:
11278002
Filing Dt:
03/30/2006
Publication #:
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
12
Patent #:
NONE
Issue Dt:
Application #:
11279741
Filing Dt:
04/13/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
13
Patent #:
NONE
Issue Dt:
Application #:
11307317
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
14
Patent #:
NONE
Issue Dt:
Application #:
11307349
Filing Dt:
02/01/2006
Publication #:
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING DIE-ATTACH PAD WITH ELEVATED BONDLINE THICKNESS
15
Patent #:
NONE
Issue Dt:
Application #:
11307498
Filing Dt:
02/09/2006
Publication #:
Pub Dt:
05/17/2007
Title:
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM
16
Patent #:
NONE
Issue Dt:
Application #:
11379018
Filing Dt:
04/17/2006
Publication #:
Pub Dt:
10/18/2007
Title:
MULTICHIP PACKAGE SYSTEM
17
Patent #:
Issue Dt:
09/02/2008
Application #:
11379097
Filing Dt:
04/18/2006
Publication #:
Pub Dt:
10/18/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
18
Patent #:
Issue Dt:
03/04/2008
Application #:
11379740
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
08/24/2006
Title:
DUAL ROW LEADFRAME AND FABRICATION METHOD
19
Patent #:
NONE
Issue Dt:
Application #:
11380587
Filing Dt:
04/27/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
20
Patent #:
NONE
Issue Dt:
Application #:
11383802
Filing Dt:
05/17/2006
Publication #:
Pub Dt:
11/22/2007
Title:
SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
21
Patent #:
NONE
Issue Dt:
Application #:
11388755
Filing Dt:
03/24/2006
Publication #:
Pub Dt:
09/28/2006
Title:
Flip chip interconnection having narrow interconnection sites on the substrate
22
Patent #:
Issue Dt:
09/08/2015
Application #:
11420853
Filing Dt:
05/30/2006
Publication #:
Pub Dt:
11/30/2006
Title:
Epoxy Bump for Overhang Die
23
Patent #:
NONE
Issue Dt:
Application #:
11435555
Filing Dt:
05/16/2006
Publication #:
Pub Dt:
11/16/2006
Title:
Flip chip interconnect solder mask
24
Patent #:
NONE
Issue Dt:
Application #:
11458065
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
25
Patent #:
NONE
Issue Dt:
Application #:
11469307
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
01/04/2007
Title:
BUMP FOR OVERHANG DEVICE
26
Patent #:
NONE
Issue Dt:
Application #:
11532508
Filing Dt:
09/15/2006
Publication #:
Pub Dt:
03/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
27
Patent #:
Issue Dt:
04/20/2010
Application #:
11536544
Filing Dt:
09/28/2006
Publication #:
Pub Dt:
01/25/2007
Title:
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
28
Patent #:
NONE
Issue Dt:
Application #:
11672910
Filing Dt:
02/08/2007
Publication #:
Pub Dt:
08/14/2008
Title:
SEMICONDUCTOR PACKAGE WIRE BONDING
29
Patent #:
NONE
Issue Dt:
Application #:
11749712
Filing Dt:
05/16/2007
Publication #:
Pub Dt:
11/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE
30
Patent #:
NONE
Issue Dt:
Application #:
11767820
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE
31
Patent #:
Issue Dt:
04/06/2010
Application #:
11772776
Filing Dt:
07/02/2007
Publication #:
Pub Dt:
12/06/2007
Title:
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
32
Patent #:
Issue Dt:
05/03/2016
Application #:
11857188
Filing Dt:
09/18/2007
Publication #:
Pub Dt:
03/19/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE
33
Patent #:
Issue Dt:
09/11/2018
Application #:
11949282
Filing Dt:
12/03/2007
Publication #:
Pub Dt:
06/04/2009
Title:
Wafer Level Package Integration and Method
34
Patent #:
NONE
Issue Dt:
Application #:
11964397
Filing Dt:
12/26/2007
Publication #:
Pub Dt:
07/02/2009
Title:
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
35
Patent #:
NONE
Issue Dt:
Application #:
12046761
Filing Dt:
03/12/2008
Publication #:
Pub Dt:
09/17/2009
Title:
Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
36
Patent #:
NONE
Issue Dt:
Application #:
12055612
Filing Dt:
03/26/2008
Publication #:
Pub Dt:
10/01/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION
37
Patent #:
Issue Dt:
01/12/2016
Application #:
12056402
Filing Dt:
03/27/2008
Publication #:
Pub Dt:
10/01/2009
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
38
Patent #:
NONE
Issue Dt:
Application #:
12062403
Filing Dt:
04/03/2008
Publication #:
Pub Dt:
10/08/2009
Title:
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
39
Patent #:
NONE
Issue Dt:
Application #:
12122639
Filing Dt:
05/16/2008
Publication #:
Pub Dt:
11/19/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
40
Patent #:
Issue Dt:
09/01/2015
Application #:
12136682
Filing Dt:
06/10/2008
Publication #:
Pub Dt:
12/10/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER GROUNDED THROUGH METAL PILLARS FORMED IN PERIPHERAL REGION OF THE SEMICONDUCTOR
41
Patent #:
Issue Dt:
03/22/2016
Application #:
12182132
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
02/04/2010
Title:
RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM
42
Patent #:
Issue Dt:
04/06/2010
Application #:
12191542
Filing Dt:
08/14/2008
Publication #:
Pub Dt:
12/04/2008
Title:
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
43
Patent #:
Issue Dt:
09/11/2012
Application #:
12205755
Filing Dt:
09/05/2008
Publication #:
Pub Dt:
03/11/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD OVER A HIGH-RESISTIVITY ENCAPSULANT SEPARATED FROM OTHER IPDS AND BASEBAND CIRCUIT
44
Patent #:
Issue Dt:
01/31/2017
Application #:
12209838
Filing Dt:
09/12/2008
Publication #:
Pub Dt:
03/18/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-IN PACKAGE-ON-PACKAGE STRUCTURE USING THROUGH-SILICON VIAS
45
Patent #:
Issue Dt:
03/22/2016
Application #:
12260089
Filing Dt:
10/28/2008
Publication #:
Pub Dt:
04/29/2010
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
46
Patent #:
Issue Dt:
02/09/2016
Application #:
12332253
Filing Dt:
12/10/2008
Publication #:
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD BENEATH A SEMICONDUCTOR DIE WITH DIRECT CONNECTION TO EXTERNAL DEVICES
47
Patent #:
NONE
Issue Dt:
Application #:
12407949
Filing Dt:
03/20/2009
Publication #:
Pub Dt:
09/23/2010
Title:
Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
48
Patent #:
NONE
Issue Dt:
Application #:
12408641
Filing Dt:
03/20/2009
Publication #:
Pub Dt:
09/23/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
49
Patent #:
NONE
Issue Dt:
Application #:
12412886
Filing Dt:
03/27/2009
Publication #:
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF
50
Patent #:
Issue Dt:
05/31/2016
Application #:
12483548
Filing Dt:
06/12/2009
Publication #:
Pub Dt:
12/16/2010
Title:
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF
51
Patent #:
NONE
Issue Dt:
Application #:
12493049
Filing Dt:
06/26/2009
Publication #:
Pub Dt:
12/30/2010
Title:
Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate
52
Patent #:
NONE
Issue Dt:
Application #:
12505273
Filing Dt:
07/17/2009
Publication #:
Pub Dt:
01/20/2011
Title:
Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton
53
Patent #:
Issue Dt:
01/05/2016
Application #:
12542097
Filing Dt:
08/17/2009
Publication #:
Pub Dt:
02/17/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
54
Patent #:
NONE
Issue Dt:
Application #:
12563368
Filing Dt:
09/21/2009
Publication #:
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
55
Patent #:
Issue Dt:
09/15/2015
Application #:
12617877
Filing Dt:
11/13/2009
Publication #:
Pub Dt:
05/19/2011
Title:
Method of Forming Protective Material Between Semiconductor Die Stacked on Semiconductor Wafer to Reduce Defects During Singulation
56
Patent #:
Issue Dt:
05/17/2016
Application #:
12683008
Filing Dt:
01/06/2010
Publication #:
Pub Dt:
04/29/2010
Title:
Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets
57
Patent #:
NONE
Issue Dt:
Application #:
12688124
Filing Dt:
01/15/2010
Publication #:
Pub Dt:
05/13/2010
Title:
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
58
Patent #:
Issue Dt:
01/23/2018
Application #:
12714190
Filing Dt:
02/26/2010
Publication #:
Pub Dt:
03/24/2011
Title:
Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
59
Patent #:
Issue Dt:
03/29/2016
Application #:
12714291
Filing Dt:
02/26/2010
Publication #:
Pub Dt:
09/09/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
60
Patent #:
Issue Dt:
05/31/2016
Application #:
12716269
Filing Dt:
03/02/2010
Publication #:
Pub Dt:
09/08/2011
Title:
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH SHIELDING AND METHOD OF MANUFACTURE THEREOF
61
Patent #:
NONE
Issue Dt:
Application #:
12718939
Filing Dt:
03/05/2010
Publication #:
Pub Dt:
09/08/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
62
Patent #:
Issue Dt:
11/15/2016
Application #:
12722852
Filing Dt:
03/12/2010
Publication #:
Pub Dt:
09/15/2011
Title:
CARRIER SYSTEM WITH MULTI-TIER CONDUCTIVE POSTS AND METHOD OF MANUFACTURE THEREOF
63
Patent #:
NONE
Issue Dt:
Application #:
12763378
Filing Dt:
04/20/2010
Publication #:
Pub Dt:
08/23/2012
Title:
Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
64
Patent #:
Issue Dt:
08/30/2016
Application #:
12773669
Filing Dt:
05/04/2010
Publication #:
Pub Dt:
11/10/2011
Title:
Semiconductor Device and Method of Forming Channels in Back Surface of FO-WLCSP for Heat Dissipation
65
Patent #:
NONE
Issue Dt:
Application #:
12777615
Filing Dt:
05/11/2010
Publication #:
Pub Dt:
11/18/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
66
Patent #:
Issue Dt:
08/11/2015
Application #:
12781754
Filing Dt:
05/17/2010
Publication #:
Pub Dt:
11/17/2011
Title:
METHOD OF FORMING PERFORATED OPENING IN BOTTOM SUBSTRATE OF FLIPCHIP POP ASSEMBLY TO REDUCE BLEEDING OF UNDERFILL MATERIAL
67
Patent #:
NONE
Issue Dt:
Application #:
12782164
Filing Dt:
05/18/2010
Publication #:
Pub Dt:
10/13/2011
Title:
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOF
68
Patent #:
Issue Dt:
08/15/2017
Application #:
12786008
Filing Dt:
05/24/2010
Publication #:
Pub Dt:
11/24/2011
Title:
Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP
69
Patent #:
Issue Dt:
09/01/2015
Application #:
12813335
Filing Dt:
06/10/2010
Publication #:
Pub Dt:
09/30/2010
Title:
Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof
70
Patent #:
NONE
Issue Dt:
Application #:
12819162
Filing Dt:
06/18/2010
Publication #:
Pub Dt:
12/22/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
71
Patent #:
Issue Dt:
02/04/2014
Application #:
12837562
Filing Dt:
07/16/2010
Publication #:
Pub Dt:
01/19/2012
Title:
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
72
Patent #:
Issue Dt:
03/08/2016
Application #:
12882728
Filing Dt:
09/15/2010
Publication #:
Pub Dt:
01/06/2011
Title:
Chip Scale Module Package in BGA Semiconductor Package
73
Patent #:
NONE
Issue Dt:
Application #:
12882748
Filing Dt:
09/15/2010
Publication #:
Pub Dt:
02/03/2011
Title:
Stackable Package By Using Internal Stacking Modules
74
Patent #:
NONE
Issue Dt:
Application #:
12946841
Filing Dt:
11/15/2010
Publication #:
Pub Dt:
05/17/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOF
75
Patent #:
Issue Dt:
08/20/2019
Application #:
12947414
Filing Dt:
11/16/2010
Publication #:
Pub Dt:
09/27/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FLIPCHIP INTERCONNECT STRUCTURE
76
Patent #:
Issue Dt:
02/09/2016
Application #:
12961107
Filing Dt:
12/06/2010
Publication #:
Pub Dt:
08/16/2012
Title:
Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings
77
Patent #:
Issue Dt:
05/17/2016
Application #:
12969451
Filing Dt:
12/15/2010
Publication #:
Pub Dt:
12/15/2011
Title:
Semiconductor Device and Method of Forming Flipchip Interconnection Structure with Bump on Partial Pad
78
Patent #:
Issue Dt:
09/08/2015
Application #:
12985559
Filing Dt:
01/06/2011
Publication #:
Pub Dt:
05/05/2011
Title:
Semiconductor Device with Bump Interconnection
79
Patent #:
NONE
Issue Dt:
Application #:
13038384
Filing Dt:
03/01/2011
Publication #:
Pub Dt:
09/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
80
Patent #:
NONE
Issue Dt:
Application #:
13038843
Filing Dt:
03/02/2011
Publication #:
Pub Dt:
08/30/2012
Title:
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
81
Patent #:
NONE
Issue Dt:
Application #:
13039309
Filing Dt:
03/02/2011
Publication #:
Pub Dt:
09/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
82
Patent #:
NONE
Issue Dt:
Application #:
13042457
Filing Dt:
03/07/2011
Publication #:
Pub Dt:
09/13/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHOD OF MANUFACTURE THEREOF
83
Patent #:
NONE
Issue Dt:
Application #:
13070362
Filing Dt:
03/23/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEVELING STANDOFF AND METHOD OF MANUFACTURE THEREOF
84
Patent #:
NONE
Issue Dt:
Application #:
13098419
Filing Dt:
04/30/2011
Publication #:
Pub Dt:
08/25/2011
Title:
Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame
85
Patent #:
Issue Dt:
10/04/2016
Application #:
13172680
Filing Dt:
06/29/2011
Publication #:
Pub Dt:
10/20/2011
Title:
Semiconductor Device and Method of Wafer Level Package Integration
86
Patent #:
Issue Dt:
06/02/2015
Application #:
13190339
Filing Dt:
07/25/2011
Publication #:
Pub Dt:
11/17/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE
87
Patent #:
Issue Dt:
07/14/2015
Application #:
13191318
Filing Dt:
07/26/2011
Publication #:
Pub Dt:
11/17/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
88
Patent #:
NONE
Issue Dt:
Application #:
13209837
Filing Dt:
08/15/2011
Publication #:
Pub Dt:
12/08/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
89
Patent #:
Issue Dt:
04/19/2016
Application #:
13211303
Filing Dt:
08/16/2011
Publication #:
Pub Dt:
12/08/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
90
Patent #:
Issue Dt:
12/16/2014
Application #:
13231789
Filing Dt:
09/13/2011
Publication #:
Pub Dt:
01/05/2012
Title:
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
91
Patent #:
Issue Dt:
12/30/2014
Application #:
13235413
Filing Dt:
09/18/2011
Publication #:
Pub Dt:
01/05/2012
Title:
Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
92
Patent #:
Issue Dt:
11/06/2012
Application #:
13237828
Filing Dt:
09/20/2011
Publication #:
Pub Dt:
01/12/2012
Title:
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
93
Patent #:
Issue Dt:
01/12/2016
Application #:
13242306
Filing Dt:
09/23/2011
Publication #:
Pub Dt:
03/28/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
94
Patent #:
Issue Dt:
12/27/2016
Application #:
13243474
Filing Dt:
09/23/2011
Publication #:
Pub Dt:
03/28/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF
95
Patent #:
NONE
Issue Dt:
Application #:
14341578
Filing Dt:
07/25/2014
Publication #:
Pub Dt:
11/13/2014
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
96
Patent #:
NONE
Issue Dt:
Application #:
14565731
Filing Dt:
12/10/2014
Publication #:
Pub Dt:
05/21/2015
Title:
Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die
97
Patent #:
Issue Dt:
07/26/2016
Application #:
14600825
Filing Dt:
01/20/2015
Publication #:
Pub Dt:
05/21/2015
Title:
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV
98
Patent #:
Issue Dt:
09/25/2018
Application #:
14637054
Filing Dt:
03/03/2015
Publication #:
Pub Dt:
06/25/2015
Title:
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
99
Patent #:
Issue Dt:
06/28/2016
Application #:
14682914
Filing Dt:
04/09/2015
Publication #:
Pub Dt:
07/30/2015
Title:
Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
Assignor
1
Exec Dt:
05/03/2019
Assignees
1
46429 LANDING PARKWAY
FREMONT, CALIFORNIA 94538
2
5 YISHUN STREET 23
SINGAPORE, SINGAPORE 768442
Correspondence name and address
PATENT LAW GROUP: ATKINS AND ASSOCIATES
123 W. CHANDLER HEIGHTS ROAD, #12535
CHANDLER, AZ 85248

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