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Reel/Frame:	056603/0094			Pages:	4
		Recorded:	06/16/2021
Attorney Dkt #:	CONVERSANT TO MOSAID
Conveyance:	CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 30

Patent #:	7804718	Issue Dt:	09/28/2010	Application #:	11779685	Filing Dt:	07/18/2007
Publication #:	US20080219053	Pub Dt:	09/11/2008
Title:	PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY

Patent #:	7646636	Issue Dt:	01/12/2010	Application #:	11829410	Filing Dt:	07/27/2007
Publication #:	US20080198651	Pub Dt:	08/21/2008
Title:	NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION

Patent #:	7904639	Issue Dt:	03/08/2011	Application #:	11840692	Filing Dt:	08/17/2007
Publication #:	US20080052449	Pub Dt:	02/28/2008
Title:	MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM

Patent #:	9116764	Issue Dt:	08/25/2015	Application #:	11873330	Filing Dt:	10/16/2007
Publication #:	US20080263116	Pub Dt:	10/23/2008
Title:	BALANCED PSEUDO-RANDOM BINARY SEQUENCE GENERATOR

Patent #:	7834654	Issue Dt:	11/16/2010	Application #:	12134451	Filing Dt:	06/06/2008
Publication #:	US20080303546	Pub Dt:	12/11/2008
Title:	DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Patent #:	7826294	Issue Dt:	11/02/2010	Application #:	12275701	Filing Dt:	11/21/2008
Publication #:	US20090073768	Pub Dt:	03/19/2009
Title:	MEMORY WITH OUTPUT CONTROL

Patent #:	8045377	Issue Dt:	10/25/2011	Application #:	12635280	Filing Dt:	12/10/2009
Publication #:	US20100174854	Pub Dt:	07/08/2010
Title:	NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION

Patent #:	8842472	Issue Dt:	09/23/2014	Application #:	12785099	Filing Dt:	05/21/2010
Publication #:	US20100226183	Pub Dt:	09/09/2010
Title:	PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY

Patent #:	8199598	Issue Dt:	06/12/2012	Application #:	12882931	Filing Dt:	09/15/2010
Publication #:	US20110002171	Pub Dt:	01/06/2011
Title:	MEMORY WITH OUTPUT CONTROL

Patent #:	8035413	Issue Dt:	10/11/2011	Application #:	12915796	Filing Dt:	10/29/2010
Publication #:	US20110043246	Pub Dt:	02/24/2011
Title:	DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Patent #:	8139414	Issue Dt:	03/20/2012	Application #:	13091479	Filing Dt:	04/21/2011
Publication #:	US20110194351	Pub Dt:	08/11/2011
Title:	SOURCE SIDE ASYMMETRICAL PRECHARGE PROGRAMMING SCHEME

Patent #:	8391064	Issue Dt:	03/05/2013	Application #:	13239813	Filing Dt:	09/22/2011
Publication #:	US20120023285	Pub Dt:	01/26/2012
Title:	NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION

Patent #:	8847623	Issue Dt:	09/30/2014	Application #:	13248330	Filing Dt:	09/29/2011
Publication #:	US20120019282	Pub Dt:	01/26/2012
Title:	DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Patent #:	8843694	Issue Dt:	09/23/2014	Application #:	13302413	Filing Dt:	11/22/2011
Publication #:	US20120066442	Pub Dt:	03/15/2012
Title:	SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES

Patent #:	8537617	Issue Dt:	09/17/2013	Application #:	13365913	Filing Dt:	02/03/2012
Publication #:	US20120262986	Pub Dt:	10/18/2012
Title:	SOURCE SIDE ASYMMETRICAL PRECHARGE PROGRAMMING SCHEME

Patent #:	8427897	Issue Dt:	04/23/2013	Application #:	13463339	Filing Dt:	05/03/2012
Publication #:	US20120215974	Pub Dt:	08/23/2012
Title:	MEMORY WITH OUTPUT CONTROL

Patent #:	8553457	Issue Dt:	10/08/2013	Application #:	13757250	Filing Dt:	02/01/2013
Publication #:	US20130141973	Pub Dt:	06/06/2013
Title:	NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION

Patent #:	8654601	Issue Dt:	02/18/2014	Application #:	13867437	Filing Dt:	04/22/2013
Publication #:	US20130229874	Pub Dt:	09/05/2013
Title:	MEMORY WITH OUTPUT CONTROL

Patent #:	8767461	Issue Dt:	07/01/2014	Application #:	14022805	Filing Dt:	09/10/2013
Publication #:	US20140010019	Pub Dt:	01/09/2014
Title:	NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION

Patent #:	9257193	Issue Dt:	02/09/2016	Application #:	14156047	Filing Dt:	01/15/2014
Publication #:	US20140133242	Pub Dt:	05/15/2014
Title:	MEMORY WITH OUTPUT CONTROL

Patent #:	9836391	Issue Dt:	12/05/2017	Application #:	14457567	Filing Dt:	08/12/2014
Publication #:	US20150046639	Pub Dt:	02/12/2015
Title:	SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES

Patent #:	9300291	Issue Dt:	03/29/2016	Application #:	14499275	Filing Dt:	09/29/2014
Publication #:	US20150008956	Pub Dt:	01/08/2015
Title:	DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Patent #:	9524783	Issue Dt:	12/20/2016	Application #:	14984303	Filing Dt:	12/30/2015
Publication #:	US20160211026	Pub Dt:	07/21/2016
Title:	FLASH MEMORY SYSTEM

Patent #:	9779804	Issue Dt:	10/03/2017	Application #:	15345552	Filing Dt:	11/08/2016
Publication #:	US20170076789	Pub Dt:	03/16/2017
Title:	FLASH MEMORY SYSTEM

Patent #:	10608634	Issue Dt:	03/31/2020	Application #:	15457680	Filing Dt:	03/13/2017
Publication #:	US20180367140	Pub Dt:	12/20/2018
Title:	DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Patent #:	9966133	Issue Dt:	05/08/2018	Application #:	15692206	Filing Dt:	08/31/2017
Publication #:	US20170365333	Pub Dt:	12/21/2017
Title:	FLASH MEMORY DEVICE

Patent #:	9972381	Issue Dt:	05/15/2018	Application #:	15868219	Filing Dt:	01/11/2018
Publication #:	US20180137912	Pub Dt:	05/17/2018
Title:	MEMORY WITH OUTPUT CONTROL

Patent #:	10224098	Issue Dt:	03/05/2019	Application #:	15937937	Filing Dt:	03/28/2018
Publication #:	US20180261282	Pub Dt:	09/13/2018
Title:	NON-VOLATILE MEMORY DEVICE

Patent #:	10679695	Issue Dt:	06/09/2020	Application #:	16249482	Filing Dt:	01/16/2019
Publication #:	US20190214077	Pub Dt:	07/11/2019
Title:	NON-VOLATILE MEMORY DEVICE

Patent #:	10985757	Issue Dt:	04/20/2021	Application #:	16795786	Filing Dt:	02/20/2020
Publication #:	US20200266818	Pub Dt:	08/20/2020
Title:	DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Assignor

CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Exec Dt:

04/01/2021

Assignee

MOSAID TECHNOLOGIES INCORPORATED

515 LEGGET DRIVE

SUITE 704

OTTAWA, CANADA K2K 3G4

Correspondence name and address
	CONVERSANT IP MANAGEMENT CORP.
	5830 GRANITE PARKWAY #100-247
	SUITE 247
	PLANO, TX 75024

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