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Reel/Frame:012852/0109   Pages: 15
Recorded: 05/06/2002
Conveyance: SECURITY AGREEMENT
Total properties: 48
1
Patent #:
6069497
Issue Dt:
05/30/2000
Application #:
09019244
Filing Dt:
02/05/1998
Title:
METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING 1 OF N SIGNALS
2
Patent #:
6066965
Issue Dt:
05/23/2000
Application #:
09019355
Filing Dt:
02/05/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT USING 1 OF 4 SIGNALS
3
Patent #:
6202194
Issue Dt:
03/13/2001
Application #:
09073478
Filing Dt:
05/06/1998
Title:
METHOD AND APPARATUS FOR ROUTING 1 OF N SIGNALS
4
Patent #:
6211456
Issue Dt:
04/03/2001
Application #:
09073479
Filing Dt:
05/06/1998
Title:
METHOD AND APPARATUS FOR ROUTING 1 OF 4 SIGNALS
5
Patent #:
6173299
Issue Dt:
01/09/2001
Application #:
09120771
Filing Dt:
07/22/1998
Title:
A METHOD AND APPARATUS FOR SELECTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
6
Patent #:
6185593
Issue Dt:
02/06/2001
Application #:
09120775
Filing Dt:
07/22/1998
Title:
METHOD AND APPARATUS FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
7
Patent #:
6151615
Issue Dt:
11/21/2000
Application #:
09120776
Filing Dt:
07/22/1998
Title:
METHOD AND APPARATUS FOR FORMATTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
8
Patent #:
6175847
Issue Dt:
01/16/2001
Application #:
09120814
Filing Dt:
07/22/1998
Title:
SHIFTING FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
9
Patent #:
6209076
Issue Dt:
03/27/2001
Application #:
09122504
Filing Dt:
07/24/1998
Title:
METHOD AND APPARATUS FOR TW0-STAGE ADDRESS GENERATION
10
Patent #:
6404233
Issue Dt:
06/11/2002
Application #:
09123742
Filing Dt:
07/28/1998
Title:
METHOD AND APPARATUS FOR LOGIC CIRCUIT TRANSITION DETECTION
11
Patent #:
6088830
Issue Dt:
07/11/2000
Application #:
09124207
Filing Dt:
07/28/1998
Title:
METHOD AND APPARATUS FOR LOGIC CIRCUIT SPEED DETECTION
12
Patent #:
6069836
Issue Dt:
05/30/2000
Application #:
09150162
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY WORD LINE GENERATION
13
Patent #:
6046931
Issue Dt:
04/04/2000
Application #:
09150258
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY OUTPUT INTERFACE
14
Patent #:
6118716
Issue Dt:
09/12/2000
Application #:
09150389
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR AN ADDRESS TRIGGERED RAM CIRCUIT
15
Patent #:
6223199
Issue Dt:
04/24/2001
Application #:
09150575
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY HPG GATE
16
Patent #:
6219686
Issue Dt:
04/17/2001
Application #:
09150717
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY SUM/HPG ADDER/SUBTRACTOR GATE
17
Patent #:
6219687
Issue Dt:
04/17/2001
Application #:
09150720
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY SUM/HPG GATE
18
Patent #:
6216146
Issue Dt:
04/10/2001
Application #:
09150829
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY ADDER GATE
19
Patent #:
6118304
Issue Dt:
09/12/2000
Application #:
09179330
Filing Dt:
10/27/1998
Title:
METHOD AND APPARATUS FOR LOGIC SYNCHRONIZATION
20
Patent #:
6233707
Issue Dt:
05/15/2001
Application #:
09179626
Filing Dt:
10/27/1998
Title:
METHOD AND APPARATUS THAT ALLOWS THE LOGIC STATE OF A LOGIC GATE TO BE TESTED WHEN STOPPING OR STARTING THE LOGIC GATE'S CLOCK
21
Patent #:
6288589
Issue Dt:
09/11/2001
Application #:
09179745
Filing Dt:
10/27/1998
Title:
METHOD AND APPARATUS FOR GENERATING CLOCK SIGNALS
22
Patent #:
6275838
Issue Dt:
08/14/2001
Application #:
09181405
Filing Dt:
10/28/1998
Title:
METHOD AND APPARATUS FOR AN ENHANCED FLOATING POINT UNIT WITH GRAPHICS AND INTEGER CAPABILITIES
23
Patent #:
6275841
Issue Dt:
08/14/2001
Application #:
09186843
Filing Dt:
11/05/1998
Title:
1 OF 4 MULTIPLIER
24
Patent #:
6272653
Issue Dt:
08/07/2001
Application #:
09191813
Filing Dt:
11/13/1998
Title:
METHOD AND APPARATUS FOR BUILT-IN SELF-TEST OF LOGIC CIRCUITRY
25
Patent #:
6301597
Issue Dt:
10/09/2001
Application #:
09195024
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR SATURATION IN AN N-NARY ADDER/SUBTRACTOR
26
Patent #:
6272514
Issue Dt:
08/07/2001
Application #:
09195751
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR INTERRUPTION OF CARRY PROPAGATION ON PARTITION BOUNDARIES
27
Patent #:
6301600
Issue Dt:
10/09/2001
Application #:
09195752
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR DYNAMIC PARTITIONABLE SATURATING ADDER/SUBTRACTOR
28
Patent #:
6334183
Issue Dt:
12/25/2001
Application #:
09195757
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR HANDLING PARTIAL REGISTER ACCESSES
29
Patent #:
6370632
Issue Dt:
04/09/2002
Application #:
09195758
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS THAT ENFORCES A REGIONAL MEMORY MODEL IN HIERARCHICAL MEMORY SYSTEMS
30
Patent #:
6260131
Issue Dt:
07/10/2001
Application #:
09195779
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR TLB MEMORY ORDERING
31
Patent #:
6269387
Issue Dt:
07/31/2001
Application #:
09206463
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR 3-STAGE 32-BIT ADDER/SUBSTRACTOR
32
Patent #:
6324239
Issue Dt:
11/27/2001
Application #:
09206539
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR A 1 OF 4 SHIFTER
33
Patent #:
6154120
Issue Dt:
11/28/2000
Application #:
09206631
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY EQUALITY COMPARATOR
34
Patent #:
6347327
Issue Dt:
02/12/2002
Application #:
09206830
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR N-NARY INCREMENTOR
35
Patent #:
6295622
Issue Dt:
09/25/2001
Application #:
09206900
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY TEST PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
36
Patent #:
6429795
Issue Dt:
08/06/2002
Application #:
09206905
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
37
Patent #:
6216147
Issue Dt:
04/10/2001
Application #:
09206906
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY MAGNITUDE COMPARATOR
38
Patent #:
6104642
Issue Dt:
08/15/2000
Application #:
09207806
Filing Dt:
12/09/1998
Title:
METHOD AND APPARATUS FOR 1 OF 4 REGISTER FILE DESIGN
39
Patent #:
6107835
Issue Dt:
08/22/2000
Application #:
09209207
Filing Dt:
12/10/1998
Title:
A METHOD AND APPARATUS FOR A LOGIC CIRCUIT WITH CONSTANT POWER CONSUMPTION
40
Patent #:
6334136
Issue Dt:
12/25/2001
Application #:
09209935
Filing Dt:
12/11/1998
Title:
DYNAMIC 3-LEVEL PARTIAL RESULT MERGE ADDER
41
Patent #:
6124735
Issue Dt:
09/26/2000
Application #:
09209967
Filing Dt:
12/10/1998
Title:
METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING CAPACITANCE ISOLATION
42
Patent #:
6345381
Issue Dt:
02/05/2002
Application #:
09210024
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR A LOGIC CIRCUIT DESIGN TOOL
43
Patent #:
6289497
Issue Dt:
09/11/2001
Application #:
09210408
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR N-NARY HARDWARE DESCRIPTION LANGUAGE
44
Patent #:
6367065
Issue Dt:
04/02/2002
Application #:
09210410
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR N-NARY LOGIC CIRCUIT DESIGN TOOL WITH PRECHARGE CIRCUIT EVALUATION
45
Patent #:
6360315
Issue Dt:
03/19/2002
Application #:
09373516
Filing Dt:
08/12/1999
Title:
METHOD AND APPARATUS THAT SUPPORTS MULTIPLE ASSIGNMENT CODE
46
Patent #:
6445213
Issue Dt:
09/03/2002
Application #:
09844686
Filing Dt:
04/27/2001
Publication #:
US20020067187
Pub Dt:
06/06/2002
Title:
METHOD FOR CALCULATING DYNAMIC LOGIC BLOCK PROPAGATION DELAY TARGETS USING TIME BORROWING
47
Patent #:
6728654
Issue Dt:
04/27/2004
Application #:
09965945
Filing Dt:
09/28/2001
Publication #:
US20030023396
Pub Dt:
01/30/2003
Title:
RANDOM NUMBER INDEXING METHOD AND APPARATUS THAT ELIMINATES SOFTWARE CALL SEQUENCE DEPENDENCY
48
Patent #:
7099812
Issue Dt:
08/29/2006
Application #:
09966049
Filing Dt:
09/28/2001
Publication #:
US20020040285
Pub Dt:
04/04/2002
Title:
GRID THAT TRACKS THE OCCURRENCE OF A N-DIMENSIONAL MATRIX OF COMBINATORIAL EVENTS IN A SIMULATION USING A LINEAR INDEX
Assignor
1
INTRINSITY, INC.
Exec Dt:
04/05/2002
Assignee
1
ADAMS CAPITAL MANAGEMENT III LP
500 BLACKBURN AVENUE
SEWICKLEY, PENNSYLVANIA 15143
Correspondence name and address
HAMILTON, BROOK, SMITH & REYNOLDS PC
DAVID J. THIBODEAU JR
530 VIRGINIA ROAD
P.O. BOX 9133
CONCORD, MA 01742-9133

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