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Total properties:
19
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Patent #:
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Issue Dt:
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12/23/1997
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Application #:
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08063845
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Filing Dt:
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05/19/1993
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Title:
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INSTRUCTION CACHE SYSTEM FOR IMPLEMENTING PROGRAMS HAVING NON- SEQUENTIAL INSTRUCTIONS AND METHOD OF IMPLEMENTING SAME
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Patent #:
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Issue Dt:
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06/17/1997
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Application #:
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08257968
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Filing Dt:
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06/10/1994
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Title:
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BIT ERROR PERFORMANCE OF A FREQUENCY HOPPING, RADIO COMMUNICATION SYSTEM
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Patent #:
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Issue Dt:
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06/04/1996
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Application #:
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08298988
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Filing Dt:
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08/31/1994
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Title:
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MEMORY SUBSYSTEMS HAVING LOOK-AHEAD INSTRUCTION PREFETCH BUFFERS AND INTELLIGENT POSTED WRITE BUFFERS FOR INCREASING THE THROUGHPUT OF DIGITAL COMPUTER SYSTEMS
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08369601
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Filing Dt:
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01/06/1995
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Title:
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DUAL PURPOSE SECURITY ARCHITECTURE WITH PROTECTED INTERNAL OPERATING SYSTEM
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Patent #:
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Issue Dt:
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01/02/1996
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Application #:
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08433829
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Filing Dt:
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05/04/1995
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Title:
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FLOATING-POINT PROCESSOR WITH APPARENT-PRECISION BASED SELECTION OF EXECUTION-PRECISION
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08757430
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Filing Dt:
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11/27/1996
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Title:
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CIRCUIT ARRANGEMENT FOR TRANSLATING PLATFORM-INDEPENDENT INSTRUCTIONS FOR EXECUTION ON A HARDWARE PLATFORM AND METHOD THEREOF
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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08757592
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Filing Dt:
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11/27/1996
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Title:
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STACK CACHE FOR STACK-BASED PROCESSOR AND METHOD THEREOF
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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08799099
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Filing Dt:
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02/11/1997
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Title:
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INTELLIGENT POWER MANAGEMENT INTERFACE FOR COMPUTER SYSTEM HARDWARE
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08804342
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Filing Dt:
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02/21/1997
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Title:
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DATA COMMUNICATIONS WITH PROCESSOR-ASSERTABLE ADDRESSES MAPPED TO PERIPHERAL-ACCESSIBLE-ADDRESSES-TIMES-COMMAND PRODUCT SPACE
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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08825661
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Filing Dt:
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04/03/1997
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Title:
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DIRECT MEMORY ACCESS CONTROLLER WITH FULL READ/WRITE CAPABILITY
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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08961965
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Filing Dt:
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10/31/1997
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Title:
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COMPUTER SYSTEM CACHE MEMORY AND PROCESS FOR CACHE ENRY REPLACEMENT WITH SELECTIVE LOCKING OF ELEMENTS IN DIFFERENT WAYS AND GROUPS
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09241175
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Filing Dt:
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02/01/1999
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Title:
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POWER-ON-RESET LOGIC WITH SECURE POWER DOWN CAPABILITY
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09241176
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Filing Dt:
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02/01/1999
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Title:
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INTEGRATION OF SECURITY MODULES ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/25/2001
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Application #:
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09283171
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND ARRANGEMENT FOR CONTROLLING MULTIPLY-ACTIVATED TEST ACCESS PORT CONTROL MODULES
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09283648
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND ARRANGEMENT FOR HIERARCHICAL CONTROL OF MULTIPLE TEST ACCESS PORT CONTROL MODULES
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09283809
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND ARRANGEMENT FOR CONTROLLING MULTIPLE TEST ACCESS PORT CONTROL MODULES
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09337089
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Filing Dt:
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06/21/1999
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Title:
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SET-ASSOCIATIVE CACHE-MANAGEMENT METHOD WITH PARALLEL AND SINGLE-SET SEQUENTIAL READS
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09797644
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Filing Dt:
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03/01/2001
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Publication #:
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Pub Dt:
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07/12/2001
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Title:
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Set-associative cache-management method with parallel and single-set sequential reads
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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09895581
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Filing Dt:
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06/29/2001
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Title:
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CACHE MANAGEMENT INSTRUCTIONS
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