Total properties:
26
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Patent #:
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Issue Dt:
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02/27/1996
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Application #:
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08252284
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Filing Dt:
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05/31/1994
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Title:
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REDUNDANCY SCHEME FOR MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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09/26/1995
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Application #:
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08297723
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Filing Dt:
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08/26/1994
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Title:
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FAST VOLTAGE EQUILIBRATION OF COMPLEMENTARY DATA LINES FOLLOWING WRITE CYCLE IN MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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08/13/1996
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Application #:
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08438148
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Filing Dt:
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05/09/1995
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Title:
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FAST VOLTAGE EQUILIBRATION OF DIFFERENTIAL DATA LINES
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Patent #:
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Issue Dt:
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11/11/1997
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Application #:
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08630283
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Filing Dt:
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04/10/1996
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Title:
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POWER BUSSING LAYOUT FOR MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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04/07/1998
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Application #:
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08630310
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Filing Dt:
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04/10/1996
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Title:
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WORD LINE DRIVER CIRCUIT
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08656165
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Filing Dt:
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05/31/1996
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Title:
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SHARED BOOTSTRAP CIRCUIT
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08890584
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Filing Dt:
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07/09/1997
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Title:
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SELF ADJUSTING DELAY CIRCUIT AND METHOD FOR COMPENSATING SENSE AMPLIFIER CLOCK TIMING
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09199884
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Filing Dt:
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11/24/1998
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Title:
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DISABLING A DEFECTIVE ELEMENT IN AN INTEGRATED CIRCUIT DEVICE HAVING REDUNDANT ELEMENTS
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09285232
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Filing Dt:
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04/01/1999
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Title:
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BIT LINE CROSS-OVER LAYOUT ARRANGEMENT
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09287948
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Filing Dt:
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04/07/1999
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Title:
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DISABLING A DECODER FOR A DEFECTIVE ELEMENT IN AN INTEGRATED CIRCUIT DEVICE HAVING REDUNDANT ELEMENTS
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09329975
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Filing Dt:
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06/10/1999
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Title:
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HIERARCHICAL DYNAMIC MEMORY ARRAY ARCHITECTURE USING READ AMPLIFIERS SEPARATE FROM BIT LINE SENSE AMPLIFIERS
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09372320
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Filing Dt:
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08/11/1999
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Title:
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DYNAMIC MEMORY ARRAY HAVING WRITE DATA APPLIED TO SELECTED BIT LINE SENSE AMPLIFIERS BEFORE SENSING TO WRITE ASSOCIATED SELECTED MEMORY CELLS
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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09439061
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Filing Dt:
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11/12/1999
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Title:
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HIGH SPEED VIDEO FRAME BUFFER
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09451042
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Filing Dt:
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11/30/1999
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Title:
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EQUILIBRATION CIRCUIT AND METHOD USING A PULSED EQUILIBRATE SIGNAL AND A LEVEL EQUILIBRATE SIGNAL
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09474351
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Filing Dt:
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12/29/1999
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Title:
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PROGRAMMABLE AND ELECTRICALLY CONFIGURABLE LATCH TIMING CIRCUIT
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|
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09499265
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Filing Dt:
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02/07/2000
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Title:
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Word line straps using two differentlayers of metal
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09502983
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Filing Dt:
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02/11/2000
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Title:
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Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09503048
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Filing Dt:
|
02/12/2000
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Title:
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Merging write cycles by comparing at least a portion of the respective write cycle addresses
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09503049
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Filing Dt:
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02/12/2000
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Title:
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Intializing memory cells within a dynamic memory array prior to performing internal memory operations
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09503050
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Filing Dt:
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02/12/2000
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Title:
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Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09503108
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Filing Dt:
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02/11/2000
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Title:
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GENERATING A TAIL CURRENT FOR A DIFFERENTIAL TRANSISTOR PAIR USING A CAPACITIVE DEVICE TO PROJECT A CURRENT FLOWING THROUGH A CURRENT SOURCE DEVICE ONTO A NODE HAVING A DIFFERENT VOLTAGE THAN THE CURRENT SOURCE DEVICE
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09503109
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Filing Dt:
|
02/11/2000
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Title:
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Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage
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Patent #:
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|
Issue Dt:
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11/27/2001
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Application #:
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09516399
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Filing Dt:
|
03/01/2000
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Title:
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APPARATUS FOR TRANSLATING A VOLTAGE
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|
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Patent #:
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|
Issue Dt:
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03/22/2005
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Application #:
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09999563
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Filing Dt:
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11/15/2001
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Title:
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INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
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Patent #:
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Issue Dt:
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12/29/2009
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Application #:
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11085770
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Filing Dt:
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03/21/2005
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Publication #:
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Pub Dt:
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07/28/2005
| | | | |
Title:
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INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
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|
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Patent #:
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|
Issue Dt:
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04/03/2012
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Application #:
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12635543
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Filing Dt:
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12/10/2009
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Publication #:
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Pub Dt:
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04/15/2010
| | | | |
Title:
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CONCURRENT MEMORY BANK ACCESS AND REFRESH RETIREMENT
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