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Total properties:
20
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11221146
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Filing Dt:
|
09/07/2005
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Publication #:
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Pub Dt:
|
03/08/2007
| | | | |
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Title:
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Structure and fabrication of an MRAM cell
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Patent #:
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NONE
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Issue Dt:
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Application #:
|
11248965
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Filing Dt:
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10/12/2005
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Publication #:
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Pub Dt:
|
04/12/2007
| | | | |
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Title:
|
Robust protective layer for MTJ devices
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Patent #:
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NONE
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Issue Dt:
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Application #:
|
11881627
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Filing Dt:
|
07/27/2007
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Publication #:
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Pub Dt:
|
01/29/2009
| | | | |
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Title:
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Spin transfer MRAM device with reduced coefficient of MTJ resistance variation
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|
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Patent #:
|
|
Issue Dt:
|
05/06/2014
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Application #:
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11904668
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Filing Dt:
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09/28/2007
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Publication #:
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Pub Dt:
|
04/02/2009
| | | | |
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Title:
|
METHOD FOR PROVIDING AFM EXCHANGE PINNING FIELDS IN MULTIPLE DIRECTIONS ON SAME SUBSTRATE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11982188
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Filing Dt:
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11/01/2007
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Publication #:
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Pub Dt:
|
05/07/2009
| | | | |
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Title:
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Magnetic field angular sensor with a full angle detection
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12316502
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Filing Dt:
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12/11/2008
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Publication #:
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Pub Dt:
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06/17/2010
| | | | |
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Title:
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PC architecture using fast NV RAM in main memory
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12321663
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Filing Dt:
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01/23/2009
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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Solid state drive controller with fast NVRAM buffer and non-volatile tables
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12454925
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Filing Dt:
|
05/26/2009
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Publication #:
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Pub Dt:
|
12/02/2010
| | | | |
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Title:
|
Read disturb-free SMT reference cell scheme
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12456324
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Filing Dt:
|
06/15/2009
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Publication #:
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Pub Dt:
|
12/16/2010
| | | | |
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Title:
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Spin torque transfer MRAM design with low switching current
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|
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Patent #:
|
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Issue Dt:
|
10/27/2015
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Application #:
|
12456923
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Filing Dt:
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06/24/2009
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Publication #:
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Pub Dt:
|
12/30/2010
| | | | |
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Title:
|
Method and apparatus for scrubbing accumulated data errors from a memory system
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|
|
|
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Patent #:
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|
Issue Dt:
|
12/17/2013
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Application #:
|
12460412
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Filing Dt:
|
07/17/2009
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Publication #:
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Pub Dt:
|
01/20/2011
| | | | |
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Title:
|
STRUCTURE AND METHOD TO FABRICATE HIGH PERFORMANCE MTJ DEVICES FOR SPIN-TRANSFER TORQUE (STT)-RAM APPLICATION
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|
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|
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Patent #:
|
NONE
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Issue Dt:
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Application #:
|
12586786
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Filing Dt:
|
09/28/2009
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Publication #:
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Pub Dt:
|
03/31/2011
| | | | |
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Title:
|
Novel process method for post plasma etch treatment
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/17/2016
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Application #:
|
12586900
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Filing Dt:
|
09/29/2009
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|
Publication #:
|
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Pub Dt:
|
03/31/2011
| | | | |
|
Title:
|
Method of high density memory fabrication
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|
|
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Patent #:
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|
Issue Dt:
|
05/13/2014
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Application #:
|
12804840
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Filing Dt:
|
07/30/2010
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|
Publication #:
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Pub Dt:
|
02/02/2012
| | | | |
|
Title:
|
COMPOSITE HARD MASK WITH UPPER SACRIFICIAL DIELECTRIC LAYER FOR THE PATTERNING AND ETCHING OF NANOMETER SIZE MRAM DEVICES
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|
|
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Patent #:
|
|
Issue Dt:
|
12/10/2013
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Application #:
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12924184
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Filing Dt:
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09/22/2010
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Publication #:
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Pub Dt:
|
03/22/2012
| | | | |
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Title:
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Replaceable, precise-tracking reference lines for memory products
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Patent #:
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|
Issue Dt:
|
01/28/2014
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Application #:
|
12924873
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Filing Dt:
|
10/07/2010
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|
Publication #:
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Pub Dt:
|
04/12/2012
| | | | |
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Title:
|
NOVEL PROCESS FOR MEMS SCANNING MIRROR WITH MASS REMOVE FROM MIRROR BACKSIDE
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Patent #:
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Issue Dt:
|
07/22/2014
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Application #:
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12930877
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Filing Dt:
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01/19/2011
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|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
|
Title:
|
MAGNETIC TUNNEL JUNCTION FOR MRAM APPLICATIONS
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|
|
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Patent #:
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|
Issue Dt:
|
04/14/2015
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Application #:
|
12931866
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Filing Dt:
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02/11/2011
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|
Publication #:
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Pub Dt:
|
08/16/2012
| | | | |
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Title:
|
Magnetic element with improved out-of-plane anisotropy for spintronic applications
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|
|
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Patent #:
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|
Issue Dt:
|
10/13/2015
|
Application #:
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13068222
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Filing Dt:
|
05/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
COMPOSITE FREE LAYER WITHIN MAGNETIC TUNNEL JUNCTION FOR MRAM APPLICATIONS
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|
|
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Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
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13136292
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Filing Dt:
|
07/28/2011
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Publication #:
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|
Pub Dt:
|
11/24/2011
| | | | |
|
Title:
|
Method and Apparatus for Scrubbing Accumulated Disturb Data Errors in an Array of SMT MRAM Memory Cells Including Rewriting Reference Bits
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|
