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414
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09131429
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Filing Dt:
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08/10/1998
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Title:
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WAFER SCALE PACKAGING SCHEME
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09246303
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Filing Dt:
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02/08/1999
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Title:
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INTERGRATED CIRCUIT HAS COMMON FUNCTION KNOWS GOOD INTERGRATED CIRCUIT DIE WITH MULTIPLE SELECTABLE FUNCTIONS
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09249252
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Filing Dt:
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02/12/1999
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Title:
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STRAIN RELEASE CONTACT SYSTEM FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09251183
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Filing Dt:
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02/17/1999
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Title:
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TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09258911
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Filing Dt:
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03/01/1999
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Title:
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HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09422174
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Filing Dt:
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10/22/1999
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Title:
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SOFTWARE PROGRAMMABLE MULTIPLE FUNCTION INTEGRATED CIRCUIT MODULE
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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09573955
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Filing Dt:
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05/19/2000
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Title:
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CHIP PACKAGE WITH CAPACITOR
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09617012
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Filing Dt:
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07/14/2000
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Title:
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Wafer scale packaging scheme
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09619017
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Filing Dt:
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07/19/2000
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Title:
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WAFER SCALE PACKAGING SCHEME
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09631041
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Filing Dt:
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08/01/2000
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Title:
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High performance system-on-chip using post passivation process and glass substrates
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09684519
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Filing Dt:
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10/10/2000
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Title:
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THERMALLY COMPLIANT PCB SUBSTRATE FOR THE APPLICATION OF CHIP SCALE PACKAGES
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09691497
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Filing Dt:
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10/18/2000
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Title:
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POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09707295
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Filing Dt:
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11/07/2000
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Title:
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METHOD AND AN APPARATUS TO ELECTROLESS PLATE A METAL LAYER WHILE ELIMINATING THE PHOTOELECTRIC EFFECT
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09721722
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Filing Dt:
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11/27/2000
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Title:
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METHOD FOR FORMING HIGH PERFORMANCE SYSTEM -ON-CHIP USING POST PASSIVATION PROCESS
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09727869
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Filing Dt:
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12/04/2000
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Publication #:
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Pub Dt:
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04/05/2001
| | | | |
Title:
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Strain release contact system for integrated circuits
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09729152
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Filing Dt:
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12/04/2000
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Publication #:
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Pub Dt:
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03/15/2001
| | | | |
Title:
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High performance sub-system design and assembly
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09760909
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Filing Dt:
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01/16/2001
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Publication #:
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Pub Dt:
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08/08/2002
| | | | |
Title:
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RELIABLE METAL BUMPS ON TOP OF I/O PADS WITH TEST PROBE MARKS
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09783384
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Filing Dt:
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02/15/2001
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Publication #:
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Pub Dt:
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08/15/2002
| | | | |
Title:
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RELIABLE METAL BUMPS ON TOP OF I/O PADS AFTER REMOVAL OF TEST PROBE MARKS
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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09798654
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Filing Dt:
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03/05/2001
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Publication #:
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Pub Dt:
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09/05/2002
| | | | |
Title:
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LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
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Patent #:
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Issue Dt:
|
06/04/2002
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Application #:
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09801327
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Filing Dt:
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03/07/2001
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Title:
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WIDE BIT MEMORY USING POST PASSIVATION INTERCONNECTION SCHEME
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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09821546
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Filing Dt:
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03/30/2001
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Publication #:
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Pub Dt:
|
10/03/2002
| | | | |
Title:
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STRUCTURE AND MANUFACTRUING METHOD OF CHIP SCALE PACKAGE
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Patent #:
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Issue Dt:
|
07/01/2003
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Application #:
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09849039
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Filing Dt:
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05/04/2001
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Title:
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HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
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Patent #:
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Issue Dt:
|
07/15/2003
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Application #:
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09858528
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Filing Dt:
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05/17/2001
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Title:
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METHODS OF IC REROUTING OPTION FOR MULTIPLE PACKAGE SYSTEM APPLICATIONS
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09932729
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Filing Dt:
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08/20/2001
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Title:
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ELECTRODE FOR ELECTROPLATING PLANAR STRUCTURES
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09945436
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Filing Dt:
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09/04/2001
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Title:
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METHOD FOR MAKING HIGH-PERFORMANCE RF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
11/04/2003
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Application #:
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09953525
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Filing Dt:
|
09/17/2001
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Title:
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METHOD MAKING A LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE
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Patent #:
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Issue Dt:
|
09/02/2003
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Application #:
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09953544
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Filing Dt:
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09/17/2001
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Title:
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STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09953610
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Filing Dt:
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09/17/2001
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Title:
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STRUCTURE OF CERAMIC PACKAGE WITH INTEGRATED PASSIVE DEVICES
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Patent #:
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Issue Dt:
|
09/06/2005
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Application #:
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09961767
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Filing Dt:
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09/21/2001
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Title:
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MULTIPLE SELECTABLE FUNCTION INTEGRATED CIRCUIT MODULE
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09970005
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Filing Dt:
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10/03/2001
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Publication #:
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Pub Dt:
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05/30/2002
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Title:
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INDUCTOR STRUCTURE FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09972639
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Filing Dt:
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10/09/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09997941
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Filing Dt:
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11/29/2001
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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Process of rectifying a wafer thickness
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09998862
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Filing Dt:
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10/24/2001
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Title:
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POST PASSIVATION METAL SCHEME FOR HIGH-PERFORMACNE INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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10004027
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Filing Dt:
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10/24/2001
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Title:
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POST PASSIVATION METAL SCHEME FOR HIGH-PERFORMANCE INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10054001
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Filing Dt:
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01/19/2002
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Title:
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THIN FILM SEMICONDUCTOR PACKAGE UTILIZING A GLASS SUBSTRATE WITH COMOSITE POLYMER/METAL INTERCONNECT LAYERS
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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10055498
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Filing Dt:
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01/22/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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INTEGRATED CHIP PACKAGE STRUCTURE USING CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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10055499
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Filing Dt:
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01/22/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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INTEGRATED CHIP PACKAGE STRUCTURE USING ORGANIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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02/21/2012
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10055560
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01/22/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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INTEGRATED CHIP PACKAGE STRUCTURE USING METAL SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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05/12/2015
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10055568
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01/22/2002
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Pub Dt:
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07/03/2003
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Title:
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CHIP PACKAGE WITH DIE AND SUBSTRATE
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NONE
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10055580
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Filing Dt:
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01/22/2002
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07/10/2003
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Title:
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Semiconductor device with metal pillar
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09/16/2003
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10058259
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01/29/2002
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06/06/2002
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Title:
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TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
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Patent #:
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02/18/2003
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Application #:
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10117888
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04/08/2002
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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AN APPARATUS TO ELECTROLESS PLATE A METAL LAYER WHILE ELIMINATING THE PHOTO ELECTRIC EFFECT
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10124388
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04/15/2002
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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07/13/2004
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Application #:
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10125226
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Filing Dt:
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04/16/2002
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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10154662
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05/24/2002
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Title:
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POST PASSIVATION METHOD FOR SEMICONDUCTOR CHIP OR WAFER
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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10156412
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Filing Dt:
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05/28/2002
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Title:
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HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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10156589
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Filing Dt:
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05/28/2002
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Title:
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A RESISTOR FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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10156590
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Filing Dt:
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05/28/2002
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Title:
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A CAPACITOR FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS STRUCTURE
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Patent #:
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08/31/2004
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10174357
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Filing Dt:
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06/17/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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METHOD OF FABRICATING CYLINDRICAL BONDING STRUCTURE
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06/08/2004
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10174462
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06/17/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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INTEGRATED CHIP PACKAGE STRUCTURE USING SILICON SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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05/11/2004
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Application #:
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10278106
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Filing Dt:
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10/22/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
Title:
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POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10279267
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10/24/2002
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Title:
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THERMAL COMPLIANT SEMICONDUCTOR CHIP WIRING STRUCTURE FOR CHIP SCALE PACKAGING
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05/24/2005
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10303451
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11/25/2002
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Pub Dt:
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04/17/2003
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Title:
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CAPACITOR FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION DEVICE
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10/12/2004
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10336871
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01/06/2003
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07/08/2004
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Title:
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METHOD OF METAL SPUTTERING FOR INTEGRATED CIRCUIT METAL ROUTING
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09/28/2004
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10337668
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01/06/2003
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Publication #:
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Pub Dt:
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06/19/2003
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Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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03/02/2004
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10337673
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01/06/2003
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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05/16/2006
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10371505
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02/21/2003
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Pub Dt:
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07/10/2003
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Title:
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MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS
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09/14/2004
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10371506
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02/21/2003
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07/03/2003
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Title:
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PRIMARY CHIPS BONDED TO A PRINTED CIRCUIT BOARD SUPPORTING A SECONDARY CHIP IN A CHIP-ON-CHIP CONNECTION
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07/03/2012
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10382699
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03/05/2003
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08/07/2003
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Title:
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METHOD FOR FABRICATING CIRCUITRY COMPONENT
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04/15/2008
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10385953
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03/11/2003
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09/11/2003
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Title:
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SOFTWARE PROGRAMMABLE MULTIPLE FUNCTION INTEGRATED CIRCUIT MODULE
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11/15/2005
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10389543
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03/14/2003
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09/11/2003
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Title:
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TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
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04/17/2007
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10420595
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04/22/2003
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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ELECTRONIC DEVICE AND CHIP PACKAGE
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05/27/2008
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10420596
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04/22/2003
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
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09/20/2011
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10434142
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05/08/2003
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04/15/2004
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Title:
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METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
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10/30/2007
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10434524
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05/08/2003
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Pub Dt:
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04/15/2004
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FABRICATION OF WIRE BOND PADS OVER UNDERLYING ACTIVE DEVICES, PASSIVE DEVICES AND /OR DIELECTRIC LAYERS IN INTEGRATED CIRCUITS
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12/23/2008
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10437333
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05/13/2003
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Pub Dt:
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10/30/2003
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Title:
|
MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS
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|
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10437355
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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10/23/2003
| | | | |
Title:
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MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS
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Patent #:
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Issue Dt:
|
05/15/2012
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Application #:
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10445558
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Filing Dt:
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05/27/2003
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
Title:
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HIGH PERFORMANCE SYSTEM-ON-CHIP INDUCTOR USING POST PASSIVATION PROCESS
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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10445559
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Filing Dt:
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05/27/2003
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Publication #:
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Pub Dt:
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02/12/2004
| | | | |
Title:
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HIGH PERFORMANCE SYSTEM-ON-CHIP PASSIVE DEVICE USING POST PASSIVATION PROCESS
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Patent #:
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Issue Dt:
|
03/22/2005
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Application #:
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10445560
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Filing Dt:
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05/27/2003
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Publication #:
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Pub Dt:
|
01/29/2004
| | | | |
Title:
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HIGH PERFORMANCE SYSTEM-ON-CHIP DISCRETE COMPONENTS USING POST PASSIVATION PROCESS
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|
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Patent #:
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Issue Dt:
|
09/17/2013
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Application #:
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10454972
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Filing Dt:
|
06/04/2003
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Publication #:
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Pub Dt:
|
11/06/2003
| | | | |
Title:
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METHOD FOR FABRICATING CHIP PACKAGE WITH DIE AND SUBSTRATE
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Patent #:
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Issue Dt:
|
07/27/2004
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Application #:
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10462251
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Filing Dt:
|
06/16/2003
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Publication #:
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Pub Dt:
|
11/13/2003
| | | | |
Title:
|
ELECTRODE FOR ELECTROPLATING PLANAR STRUCTURES
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Patent #:
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Issue Dt:
|
10/16/2007
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Application #:
|
10614928
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Filing Dt:
|
07/08/2003
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Publication #:
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|
Pub Dt:
|
02/05/2004
| | | | |
Title:
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STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD
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Patent #:
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Issue Dt:
|
03/31/2009
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Application #:
|
10638018
|
Filing Dt:
|
08/08/2003
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Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
Title:
|
CIRCUITRY COMPONENT WITH METAL LAYER OVER DIE AND EXTENDING TO PLACE NOT OVER DIE
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|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10638454
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Filing Dt:
|
08/11/2003
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Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
Title:
|
LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE
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|
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Patent #:
|
|
Issue Dt:
|
10/28/2008
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Application #:
|
10653628
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Filing Dt:
|
09/02/2003
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Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
Title:
|
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
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Application #:
|
10685872
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Filing Dt:
|
10/15/2003
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Publication #:
|
|
Pub Dt:
|
05/13/2004
| | | | |
Title:
|
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
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Application #:
|
10690250
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Filing Dt:
|
10/20/2003
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Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
Title:
|
PROCESS OF FABRICATING A CHIP STRUCTURE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10690350
|
Filing Dt:
|
10/21/2003
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Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
Title:
|
Thin film semiconductor package and method of fabrication
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|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10695630
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Filing Dt:
|
10/27/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
CHIP PACKAGE WITH MULTIPLE CHIPS CONNECTED BY BUMPS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
10710596
|
Filing Dt:
|
07/23/2004
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Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
Title:
|
CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10728150
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Filing Dt:
|
12/03/2003
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
Title:
|
ELECTRONIC COMPONENT WITH DIE AND PASSIVE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
10730834
|
Filing Dt:
|
12/08/2003
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
CHIP STRUCTURE WITH PADS HAVING BUMPS OR WIREBONDED WIRES FORMED THEREOVER OR USED TO BE TESTED THERETO
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|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
10755042
|
Filing Dt:
|
01/09/2004
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
Title:
|
INTEGRATED CHIP PACKAGE STRUCTURE USING SILICON SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
10783195
|
Filing Dt:
|
02/20/2004
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
Title:
|
POST PASSIVATION STRUCTURE FOR SEMICONDUCTOR CHIP OR WAFER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10786807
|
Filing Dt:
|
02/25/2004
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
Method for improving semiconductor wafer test accuracy
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|
|
Patent #:
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|
Issue Dt:
|
11/20/2007
|
Application #:
|
10794472
|
Filing Dt:
|
03/05/2004
|
Publication #:
|
|
Pub Dt:
|
09/02/2004
| | | | |
Title:
|
METHOD FOR FABRICATING CIRCUITRY COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
10796427
|
Filing Dt:
|
03/09/2004
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
WIREBOND PAD FOR SEMICONDUCTOR CHIP OR WAFER
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|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
10802566
|
Filing Dt:
|
03/17/2004
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
Title:
|
HIGH PERFORMANCE IC CHIP HAVING DISCRETE DECOUPLING CAPACITORS ATTACHED TO ITS IC SURFACE
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|
Patent #:
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|
Issue Dt:
|
03/18/2014
|
Application #:
|
10855086
|
Filing Dt:
|
05/27/2004
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
WAFER LEVEL PROCESSING METHOD AND STRUCTURE TO MANUFACTURE TWO KINDS OF INTERCONNECTS, GOLD AND SOLDER, ON ONE WAFER
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Patent #:
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Issue Dt:
|
01/15/2008
|
Application #:
|
10856377
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Filing Dt:
|
05/28/2004
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
Title:
|
METHOD FOR MAKING HIGH-PERFORMANCE RF INTEGRATED CIRCUITS
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|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10874704
|
Filing Dt:
|
06/22/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
BONDING STRUCTURE WITH PILLAR AND CAP
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|
|
Patent #:
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|
Issue Dt:
|
09/04/2007
|
Application #:
|
10925302
|
Filing Dt:
|
08/24/2004
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
METHOD FOR FABRICATING THERMAL COMPLIANT SEMICONDUCTOR CHIP WIRING STRUCTURE FOR CHIP SCALE PACKAGING
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10933961
|
Filing Dt:
|
09/02/2004
|
Publication #:
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|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
METHOD FOR FABRICATING CIRCUITRY COMPONENT
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|
|
Patent #:
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|
Issue Dt:
|
02/05/2013
|
Application #:
|
10935451
|
Filing Dt:
|
09/07/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
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|
Patent #:
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Issue Dt:
|
09/09/2008
|
Application #:
|
10937543
|
Filing Dt:
|
09/09/2004
|
Publication #:
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Pub Dt:
|
03/09/2006
| | | | |
Title:
|
POST PASSIVATION INTERCONNECTION PROCESS AND STRUCTURES
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|
Patent #:
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Issue Dt:
|
08/26/2008
|
Application #:
|
10948020
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Filing Dt:
|
09/23/2004
|
Publication #:
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|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
10954781
|
Filing Dt:
|
09/30/2004
|
Publication #:
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Pub Dt:
|
02/24/2005
| | | | |
Title:
|
METHOD OF METAL SPUTTERING FOR INTEGRATED CIRCUIT METAL ROUTING
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Patent #:
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Issue Dt:
|
09/18/2007
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Application #:
|
10962963
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Filing Dt:
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10/12/2004
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Title:
|
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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Patent #:
|
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Issue Dt:
|
12/16/2008
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Application #:
|
10962964
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Filing Dt:
|
10/12/2004
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Publication #:
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Pub Dt:
|
03/31/2005
| | | | |
Title:
|
RELIABLE METAL BUMPS ON TOP OF I/O PADS AFTER REMOVAL OF TEST PROBE MARKS
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