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Reel/Frame:018855/0129   Pages: 450
Recorded: 02/02/2007
Attorney Dkt #:376679
Conveyance: SECURITY AGREEMENT
Total properties: 5503
Page 45 of 56
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1
Patent #:
Issue Dt:
01/16/2007
Application #:
10902204
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/02/2006
Title:
DYNAMIC LATCH HAVING INTEGRAL LOGIC FUNCTION AND METHOD THEREFOR
2
Patent #:
Issue Dt:
12/05/2006
Application #:
10902218
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/02/2006
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF
3
Patent #:
Issue Dt:
10/10/2006
Application #:
10903784
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURE HAVING ION IMPLANT IN ONLY ONE OF THE COMPLEMENTARY DEVICES
4
Patent #:
Issue Dt:
01/22/2008
Application #:
10903841
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
INTERFACIAL LAYER FOR USE WITH HIGH K DIELECTRIC MATERIALS
5
Patent #:
NONE
Issue Dt:
Application #:
10904196
Filing Dt:
10/28/2004
Publication #:
Pub Dt:
05/26/2005
Title:
TONE DETECTION USING A CDMA RECEIVER
6
Patent #:
NONE
Issue Dt:
Application #:
10909095
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
Method of making a double gate semiconductor device with self-aligned gates and structure thereof
7
Patent #:
NONE
Issue Dt:
Application #:
10909100
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
Probe pad arrangement for an integrated circuit and method of forming
8
Patent #:
Issue Dt:
04/24/2007
Application #:
10909124
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/03/2005
Title:
SEMICONDUCTOR DEVICE WITH STRAIN RELIEVING BUMP DESIGN
9
Patent #:
Issue Dt:
01/30/2007
Application #:
10910036
Filing Dt:
08/03/2004
Publication #:
Pub Dt:
01/20/2005
Title:
METHOD FOR FORMING A BOND PAD INTERFACE
10
Patent #:
Issue Dt:
09/12/2006
Application #:
10911624
Filing Dt:
08/05/2004
Publication #:
Pub Dt:
03/17/2005
Title:
HETEROJUNCTION TUNNELING DIODES AND PROCESS FOR FABRICATING SAME
11
Patent #:
Issue Dt:
05/09/2006
Application #:
10912824
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
02/09/2006
Title:
MEMORY BIT LINE SEGMENT ISOLATION
12
Patent #:
Issue Dt:
01/09/2007
Application #:
10912825
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
02/09/2006
Title:
METHOD OF DISCHARGING A SEMICONDUCTOR DEVICE
13
Patent #:
Issue Dt:
01/30/2007
Application #:
10912979
Filing Dt:
08/05/2004
Publication #:
Pub Dt:
01/13/2005
Title:
MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
14
Patent #:
Issue Dt:
06/05/2007
Application #:
10914006
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
02/09/2006
Title:
TUNGSTEN COATED SILICON FINGERS
15
Patent #:
NONE
Issue Dt:
Application #:
10914442
Filing Dt:
08/09/2004
Publication #:
Pub Dt:
02/09/2006
Title:
Electrostatic discharge protection for an integrated circuit
16
Patent #:
Issue Dt:
07/24/2007
Application #:
10916298
Filing Dt:
08/11/2004
Publication #:
Pub Dt:
02/16/2006
Title:
PREFETCHING IN A DATA PROCESSING SYSTEM
17
Patent #:
Issue Dt:
02/13/2007
Application #:
10917891
Filing Dt:
08/13/2004
Publication #:
Pub Dt:
02/16/2006
Title:
HIGH LINEARITY AND LOW NOISE CMOS MIXER AND SIGNAL MIXING METHOD
18
Patent #:
Issue Dt:
12/04/2007
Application #:
10918457
Filing Dt:
08/16/2004
Publication #:
Pub Dt:
02/16/2006
Title:
METHOD FOR PROVIDING RAPID DELAYED FRAME ACKNOWLEDGEMENT IN A WIRELESS TRANSCEIVER
19
Patent #:
Issue Dt:
06/06/2006
Application #:
10919784
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
03/31/2005
Title:
SEMICONDUCTOR LAYER FORMATION
20
Patent #:
Issue Dt:
04/24/2007
Application #:
10919922
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
03/31/2005
Title:
TEMPLATE LAYER FORMATION
21
Patent #:
Issue Dt:
07/10/2007
Application #:
10919952
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
02/23/2006
Title:
GRADED SEMICONDUCTOR LAYER
22
Patent #:
Issue Dt:
05/09/2006
Application #:
10922436
Filing Dt:
08/19/2004
Publication #:
Pub Dt:
01/27/2005
Title:
METHOD AND STRUCTURE FOR CONTACTING AN OVERLYING ELECTRODE FOR A MAGNETOELECTRONICS ELEMENT
23
Patent #:
Issue Dt:
03/14/2006
Application #:
10924631
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
03/02/2006
Title:
CIRCUIT AND METHOD FOR CURRENT PULSE COMPENSATION
24
Patent #:
Issue Dt:
12/27/2005
Application #:
10924632
Filing Dt:
08/24/2004
Title:
SEMICONDUCTOR TRANSISTOR HAVING STRUCTURAL ELEMENTS OF DIFFERING MATERIALS AND METHOD OF FORMATION
25
Patent #:
Issue Dt:
01/23/2007
Application #:
10924650
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD AND APPARATUS FOR PERFORMANCE ENHANCEMENT IN AN ASYMMETRICAL SEMICONDUCTOR DEVICE
26
Patent #:
Issue Dt:
01/09/2007
Application #:
10925084
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
03/02/2006
Title:
TRANSISTOR STRUCTURE WITH STRESS MODIFICATION AND CAPACITIVE REDUCTION FEATURE IN A WIDTH DIRECTION AND METHOD THEREOF
27
Patent #:
Issue Dt:
10/30/2007
Application #:
10925108
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD AND APPARATUS FOR MOBILITY ENHANCEMENT IN A SEMICONDUCTOR DEVICE
28
Patent #:
Issue Dt:
06/12/2007
Application #:
10925855
Filing Dt:
08/25/2004
Publication #:
Pub Dt:
03/02/2006
Title:
RECESSED SEMICONDUCTOR DEVICE
29
Patent #:
Issue Dt:
08/22/2006
Application #:
10926121
Filing Dt:
08/25/2004
Publication #:
Pub Dt:
03/02/2006
Title:
VARIABLE IMPEDANCE OUTPUT BUFFER
30
Patent #:
Issue Dt:
11/14/2006
Application #:
10927921
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
APPLICATIONS OF A HIGH IMPEDANCE SURFACE
31
Patent #:
Issue Dt:
11/14/2006
Application #:
10927944
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
FREQUENCY SELECTIVE HIGH IMPEDANCE SURFACE
32
Patent #:
Issue Dt:
02/27/2007
Application #:
10928399
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
DATA PROCESSING SYSTEM HAVING TRANSLATION LOOKASIDE BUFFER VALID BITS WITH LOCK AND METHOD THEREFOR
33
Patent #:
Issue Dt:
06/06/2006
Application #:
10930660
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
03/02/2006
Title:
MULTILAYER CAVITY SLOT ANTENNA
34
Patent #:
Issue Dt:
09/12/2006
Application #:
10930891
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
03/02/2006
Title:
PROGRAMMING AND ERASING STRUCTURE FOR AN NVM CELL
35
Patent #:
Issue Dt:
03/27/2007
Application #:
10930892
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
03/02/2006
Title:
PROGRAMMING, ERASING, AND READING STRUCTURE FOR AN NVM CELL
36
Patent #:
NONE
Issue Dt:
Application #:
10933052
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
03/02/2006
Title:
Metal oxide semiconductor device including a shielding structure for low gate-drain capacitance
37
Patent #:
Issue Dt:
10/02/2012
Application #:
10933191
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD AND APPARATUS FOR MODIFYING AN INFORMATION UNIT USING AN ATOMIC OPERATION
38
Patent #:
Issue Dt:
07/03/2007
Application #:
10939148
Filing Dt:
09/10/2004
Publication #:
Pub Dt:
03/16/2006
Title:
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE SPACERS IN SIDEWALL REGIONS AND METHOD FOR FORMING
39
Patent #:
Issue Dt:
12/05/2006
Application #:
10940058
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/16/2006
Title:
OPEN LOOP MOTOR PARKING METHOD AND SYSTEM
40
Patent #:
Issue Dt:
11/11/2014
Application #:
10940121
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/16/2006
Title:
System and method for fetching information in response to hazard indication information
41
Patent #:
Issue Dt:
07/24/2007
Application #:
10940252
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/30/2006
Title:
METHOD AND APPARATUS FOR NON-INTRUSIVE TRACING
42
Patent #:
Issue Dt:
04/24/2007
Application #:
10943383
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL LAYER
43
Patent #:
Issue Dt:
05/02/2006
Application #:
10943579
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
MRAM SENSE AMPLIFIER HAVING A PRECHARGE CIRCUIT AND METHOD FOR SENSING
44
Patent #:
Issue Dt:
08/22/2006
Application #:
10944239
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING
45
Patent #:
Issue Dt:
02/27/2007
Application #:
10944244
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING
46
Patent #:
Issue Dt:
06/26/2007
Application #:
10944306
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER
47
Patent #:
Issue Dt:
06/08/2010
Application #:
10944310
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
SYSTEM AND METHOD FOR SPECIFYING AN IMMEDIATE VALUE IN AN INSTRUCTION
48
Patent #:
Issue Dt:
10/09/2007
Application #:
10945319
Filing Dt:
09/20/2004
Publication #:
Pub Dt:
03/23/2006
Title:
DEPOSITION AND PATTERNING OF BORON NITRIDE NANOTUBE ILD
49
Patent #:
Issue Dt:
02/13/2007
Application #:
10946675
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
02/17/2005
Title:
SEMICONDUCTOR DEVICE HAVING A MULTIPLE THICKNESS INTERCONNECT
50
Patent #:
Issue Dt:
07/26/2005
Application #:
10946758
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
02/24/2005
Title:
SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES INCLUDING A VIA WITH AN END FORMED AT A BOTTOM SURFACE OF THE DIFFUSION REGION
51
Patent #:
Issue Dt:
07/04/2006
Application #:
10946938
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
03/23/2006
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A DIELECTRIC LAYER WITH HIGH DIELECTRIC CONSTANT
52
Patent #:
Issue Dt:
03/06/2007
Application #:
10946951
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
03/23/2006
Title:
METHOD AND APPARATUS FOR PROTECTING AN INTEGRATED CIRCUIT FROM ERRONEOUS OPERATION
53
Patent #:
Issue Dt:
04/08/2008
Application #:
10949057
Filing Dt:
09/23/2004
Publication #:
Pub Dt:
03/23/2006
Title:
SEMICONDUCTOR PROCESS WITH FIRST TRANSISTOR TYPES ORIENTED IN A FIRST PLANE AND SECOND TRANSISTOR TYPES ORIENTED IN A SECOND PLANE
54
Patent #:
Issue Dt:
11/29/2005
Application #:
10950855
Filing Dt:
09/27/2004
Publication #:
Pub Dt:
02/24/2005
Title:
NON-VOLATILE MEMORY HAVING A REFERENCE TRANSISTOR
55
Patent #:
Issue Dt:
06/27/2006
Application #:
10952676
Filing Dt:
09/29/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DOUBLE GATE DEVICE HAVING A HETEROJUNCTION SOURCE/DRAIN AND STRAINED CHANNEL
56
Patent #:
Issue Dt:
04/01/2008
Application #:
10952813
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
SYSTEM AND METHOD FOR ULTRA WIDEBAND COMMUNICATIONS USING MULTIPLE CODE WORDS
57
Patent #:
Issue Dt:
03/28/2006
Application #:
10954121
Filing Dt:
09/29/2004
Publication #:
Pub Dt:
03/30/2006
Title:
METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN
58
Patent #:
Issue Dt:
07/11/2006
Application #:
10954400
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/06/2006
Title:
PLASMA ENHANCED NITRIDE LAYER
59
Patent #:
Issue Dt:
10/21/2008
Application #:
10954793
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/06/2006
Title:
APPARATUS AND METHOD FOR HIGH SPEED VOLTAGE REGULATION
60
Patent #:
Issue Dt:
10/31/2006
Application #:
10954809
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DATA PROCESSING SYSTEM WITH BUS ACCESS RETRACTION
61
Patent #:
Issue Dt:
06/05/2007
Application #:
10955219
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DEVICE AND A METHOD FOR BIASING A TRANSISTOR THAT IS CONNECTED TO A POWER CONVERTER
62
Patent #:
Issue Dt:
10/07/2008
Application #:
10955220
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
APPARATUS AND METHOD FOR PROVIDING INFORMATION TO A CACHE MODULE USING FETCH BURSTS
63
Patent #:
Issue Dt:
04/22/2008
Application #:
10955356
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/20/2006
Title:
INTEGRATED CIRCUIT FUSES HAVING CORRESPONDING STORAGE CIRCUITRY
64
Patent #:
Issue Dt:
03/04/2008
Application #:
10955558
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DATA PROCESSING SYSTEM WITH BUS ACCESS RETRACTION
65
Patent #:
Issue Dt:
11/14/2006
Application #:
10955658
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
ISOLATION TRENCH PERIMETER IMPLANT FOR THRESHOLD VOLTAGE CONTROL
66
Patent #:
Issue Dt:
11/09/2010
Application #:
10958039
Filing Dt:
10/04/2004
Publication #:
Pub Dt:
03/17/2005
Title:
METHOD AND APPARATUS FOR DATA ALLOCATION IN AN OVERLAP-ENABLED COMMUNICATION SYSTEM
67
Patent #:
Issue Dt:
09/19/2006
Application #:
10958831
Filing Dt:
10/05/2004
Publication #:
Pub Dt:
04/06/2006
Title:
WELL BIAS VOLTAGE GENERATOR
68
Patent #:
Issue Dt:
06/20/2006
Application #:
10961014
Filing Dt:
10/08/2004
Publication #:
Pub Dt:
04/13/2006
Title:
METHOD FOR FORMING A MULTI-BIT NON-VOLATILE MEMORY DEVICE
69
Patent #:
Issue Dt:
04/14/2009
Application #:
10961295
Filing Dt:
10/08/2004
Publication #:
Pub Dt:
04/13/2006
Title:
VIRTUAL GROUND MEMORY ARRAY AND METHOD THEREFOR
70
Patent #:
NONE
Issue Dt:
Application #:
10961296
Filing Dt:
10/08/2004
Publication #:
Pub Dt:
04/13/2006
Title:
Virtual ground memory array and method therefor
71
Patent #:
Issue Dt:
10/24/2006
Application #:
10962944
Filing Dt:
10/12/2004
Publication #:
Pub Dt:
04/13/2006
Title:
INTEGRATION OF MULTIPLE GATE DIELECTRICS BY SURFACE PROTECTION
72
Patent #:
Issue Dt:
09/04/2007
Application #:
10963387
Filing Dt:
10/12/2004
Publication #:
Pub Dt:
04/14/2005
Title:
DC INTERFERENCE REMOVAL IN WIRELESS COMMUNICATIONS
73
Patent #:
Issue Dt:
08/01/2006
Application #:
10964793
Filing Dt:
10/14/2004
Publication #:
Pub Dt:
04/20/2006
Title:
BAND-GAP REFERENCE CIRCUIT
74
Patent #:
Issue Dt:
06/27/2006
Application #:
10965596
Filing Dt:
10/14/2004
Publication #:
Pub Dt:
03/03/2005
Title:
SYSTEM AND METHOD FOR CACHE EXTERNAL WRITING AND WRITE SHADOWING
75
Patent #:
NONE
Issue Dt:
Application #:
10965963
Filing Dt:
10/15/2004
Publication #:
Pub Dt:
04/20/2006
Title:
Differentially nitrided gate dielectrics in CMOS fabrication process
76
Patent #:
Issue Dt:
05/02/2006
Application #:
10965964
Filing Dt:
10/15/2004
Publication #:
Pub Dt:
04/20/2006
Title:
LOW RC PRODUCT TRANSISTORS IN SOI SEMICONDUCTOR PROCESS
77
Patent #:
NONE
Issue Dt:
Application #:
10966877
Filing Dt:
10/15/2004
Publication #:
Pub Dt:
04/20/2006
Title:
Amplitude and phase compensator for BTSC encoder
78
Patent #:
Issue Dt:
05/22/2007
Application #:
10967563
Filing Dt:
10/18/2004
Publication #:
Pub Dt:
04/20/2006
Title:
LOGIC CIRCUITRY
79
Patent #:
Issue Dt:
10/03/2006
Application #:
10967898
Filing Dt:
10/18/2004
Publication #:
Pub Dt:
04/20/2006
Title:
CIRCUIT AND METHOD FOR INTERPOLATIVE DELAY
80
Patent #:
Issue Dt:
01/09/2007
Application #:
10969108
Filing Dt:
10/20/2004
Publication #:
Pub Dt:
04/20/2006
Title:
CHANNEL ORIENTATION TO ENHANCE TRANSISTOR PERFORMANCE
81
Patent #:
Issue Dt:
09/04/2007
Application #:
10969426
Filing Dt:
10/20/2004
Publication #:
Pub Dt:
04/20/2006
Title:
TEST SYSTEM FOR DEVICE CHARACTERIZATION
82
Patent #:
NONE
Issue Dt:
Application #:
10969486
Filing Dt:
10/20/2004
Publication #:
Pub Dt:
04/20/2006
Title:
Plasma impurification of a metal gate in a semiconductor fabrication process
83
Patent #:
Issue Dt:
03/21/2006
Application #:
10969634
Filing Dt:
10/20/2004
Title:
METHOD FOR FORMING A LAYER USING A PURGING GAS IN A SEMICONDUCTOR PROCESS
84
Patent #:
Issue Dt:
08/28/2007
Application #:
10970098
Filing Dt:
10/20/2004
Publication #:
Pub Dt:
04/20/2006
Title:
RADIO FREQUENCY POWER AMPLIFIER
85
Patent #:
Issue Dt:
04/29/2008
Application #:
10971657
Filing Dt:
10/22/2004
Publication #:
Pub Dt:
04/27/2006
Title:
MANUFACTURING METHOD TO CONSTRUCT SEMICONDUCTOR-ON-INSULATOR WITH CONDUCTOR LAYER SANDWICHED BETWEEN BURIED DIELECTRIC LAYER AND SEMICONDUCTOR LAYERS
86
Patent #:
Issue Dt:
12/12/2006
Application #:
10971741
Filing Dt:
10/22/2004
Publication #:
Pub Dt:
04/27/2006
Title:
SPIN-TRANSFER BASED MRAM USING ANGULAR-DEPENDENT SELECTIVITY
87
Patent #:
Issue Dt:
02/27/2007
Application #:
10973728
Filing Dt:
10/26/2004
Publication #:
Pub Dt:
04/28/2005
Title:
TRANSCONDUCTANCE AMPLIFIER
88
Patent #:
Issue Dt:
04/22/2008
Application #:
10974658
Filing Dt:
10/27/2004
Publication #:
Pub Dt:
04/27/2006
Title:
THERMALLY ENHANCED MOLDED PACKAGE FOR SEMICONDUCTORS
89
Patent #:
Issue Dt:
11/06/2007
Application #:
10975375
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
SYSTEM AND METHOD FOR PROVIDING A SINGLE-ENDED RECEIVE PORTION AND A DIFFERENTIAL TRANSMIT PORTION IN A WIRELESS TRANSCEIVER
90
Patent #:
Issue Dt:
12/05/2006
Application #:
10977003
Filing Dt:
10/27/2004
Publication #:
Pub Dt:
04/27/2006
Title:
MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME
91
Patent #:
Issue Dt:
09/11/2007
Application #:
10977010
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
GAIN CONTROL IN A SIGNAL PATH WITH SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION
92
Patent #:
NONE
Issue Dt:
Application #:
10977103
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
11/24/2005
Title:
Register unit
93
Patent #:
NONE
Issue Dt:
Application #:
10977164
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
11/24/2005
Title:
Light-emitting element drive circuit
94
Patent #:
Issue Dt:
10/30/2007
Application #:
10977226
Filing Dt:
01/18/2005
Publication #:
Pub Dt:
07/20/2006
Title:
SEMICONDUCTOR DEVICE HAVING TRENCH ISOLATION FOR DIFFERENTIAL STRESS AND METHOD THEREFOR
95
Patent #:
Issue Dt:
10/02/2007
Application #:
10977266
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
TRANSISTOR STRUCTURE WITH DUAL TRENCH FOR OPTIMIZED STRESS EFFECT AND METHOD THEREFOR
96
Patent #:
Issue Dt:
06/05/2007
Application #:
10977423
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR
97
Patent #:
NONE
Issue Dt:
Application #:
10977425
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
11/24/2005
Title:
Burst signal receiver
98
Patent #:
Issue Dt:
04/29/2008
Application #:
10977727
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
SEMICONDUCTOR STRUCTURE HAVING A METALLIC BUFFER LAYER AND METHOD FOR FORMING
99
Patent #:
Issue Dt:
07/18/2006
Application #:
10977832
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/05/2005
Title:
POWER AMPLIFIER SATURATION DETECTION AND OPERATION AT MAXIMUM POWER
100
Patent #:
Issue Dt:
04/03/2007
Application #:
10978596
Filing Dt:
11/01/2004
Publication #:
Pub Dt:
05/04/2006
Title:
BALUNS FOR MULTIPLE BAND OPERATION
Assignors
1
Exec Dt:
12/01/2006
2
Exec Dt:
12/01/2006
3
Exec Dt:
12/01/2006
4
Exec Dt:
12/01/2006
Assignee
1
390 GREENWICH STREET
NEW YORK, NEW YORK 10013
Correspondence name and address
CBCINNOVIS DBA FEDERAL RESEARCH
1023 FIFTEENTH STREET, NW, STE 401
ATTN: OLEH HERELIUK
WASHINGTON, DC 20005

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