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Reel/Frame:018855/0129   Pages: 450
Recorded: 02/02/2007
Attorney Dkt #:376679
Conveyance: SECURITY AGREEMENT
Total properties: 5503
Page 54 of 56
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1
Patent #:
NONE
Issue Dt:
Application #:
11426628
Filing Dt:
06/27/2006
Publication #:
Pub Dt:
12/27/2007
Title:
METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR
2
Patent #:
Issue Dt:
04/12/2011
Application #:
11426630
Filing Dt:
06/27/2006
Publication #:
Pub Dt:
12/27/2007
Title:
COPROCESSOR FORWARDING LOAD AND STORE INSTRUCTIONS WITH DISPLACEMENT TO MAIN PROCESSOR FOR CACHE COHERENT EXECUTION WHEN PROGRAM COUNTER VALUE FALLS WITHIN PREDETERMINED RANGES
3
Patent #:
Issue Dt:
09/28/2010
Application #:
11426633
Filing Dt:
06/27/2006
Publication #:
Pub Dt:
12/27/2007
Title:
COPROCESSOR RECEIVING TARGET ADDRESS TO PROCESS A FUNCTION AND TO SEND DATA TRANSFER INSTRUCTIONS TO MAIN PROCESSOR FOR EXECUTION TO PRESERVE CACHE COHERENCE
4
Patent #:
NONE
Issue Dt:
Application #:
11426755
Filing Dt:
06/27/2006
Publication #:
Pub Dt:
12/27/2007
Title:
REMOVING METAL USING AN OXIDIZING CHEMISTRY
5
Patent #:
Issue Dt:
01/13/2009
Application #:
11426815
Filing Dt:
06/27/2006
Publication #:
Pub Dt:
11/02/2006
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
6
Patent #:
Issue Dt:
11/06/2007
Application #:
11427610
Filing Dt:
06/29/2006
Title:
INTEGRATED CIRCUIT HAVING A MEMORY WITH LOW VOLTAGE READ/WRITE OPERATION
7
Patent #:
Issue Dt:
02/02/2010
Application #:
11427980
Filing Dt:
06/30/2006
Publication #:
Pub Dt:
01/03/2008
Title:
A METHOD OF MAKING METAL GATE TRANSISTORS
8
Patent #:
Issue Dt:
12/08/2009
Application #:
11428038
Filing Dt:
06/30/2006
Publication #:
Pub Dt:
01/03/2008
Title:
METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF
9
Patent #:
Issue Dt:
10/18/2011
Application #:
11428953
Filing Dt:
07/06/2006
Publication #:
Pub Dt:
01/17/2008
Title:
SELECTIVE UNIAXIAL STRESS MODIFICATION FOR USE WITH STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT
10
Patent #:
NONE
Issue Dt:
Application #:
11430658
Filing Dt:
05/09/2006
Publication #:
Pub Dt:
11/15/2007
Title:
Addressing scheme for microcontroller unit
11
Patent #:
Issue Dt:
05/05/2009
Application #:
11433298
Filing Dt:
05/12/2006
Publication #:
Pub Dt:
11/15/2007
Title:
PROCESS OF FORMING ELECTRONIC DEVICE INCLUDING A DENSIFIED NITRIDE LAYER ADJACENT TO AN OPENING WITHIN A SEMICONDUCTOR LAYER
12
Patent #:
Issue Dt:
09/15/2009
Application #:
11433590
Filing Dt:
05/12/2006
Publication #:
Pub Dt:
11/29/2007
Title:
FREQUENCY CORRECTION CHANNEL BURST DETECTOR IN A GSM/EDGE COMMUNICATION SYSTEM
13
Patent #:
Issue Dt:
10/21/2008
Application #:
11433998
Filing Dt:
05/15/2006
Publication #:
Pub Dt:
11/15/2007
Title:
MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
14
Patent #:
Issue Dt:
03/05/2013
Application #:
11435917
Filing Dt:
05/17/2006
Publication #:
Pub Dt:
11/22/2007
Title:
Delay configurable device and methods thereof
15
Patent #:
Issue Dt:
03/09/2010
Application #:
11435942
Filing Dt:
05/17/2006
Publication #:
Pub Dt:
12/06/2007
Title:
LOW VOLTAGE MEMORY DEVICE AND METHOD THEREOF
16
Patent #:
Issue Dt:
01/19/2010
Application #:
11435944
Filing Dt:
05/17/2006
Publication #:
Pub Dt:
02/21/2008
Title:
BIT CELL REFERENCE DEVICE AND METHODS THEREOF
17
Patent #:
Issue Dt:
08/17/2010
Application #:
11436234
Filing Dt:
05/18/2006
Publication #:
Pub Dt:
11/22/2007
Title:
HARDWARE MONITOR OF LIN TIME BUDGET
18
Patent #:
Issue Dt:
04/12/2011
Application #:
11437073
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
ELECTRICAL COMPONENT HAVING AN INDUCTOR AND A METHOD OF FORMATION
19
Patent #:
Issue Dt:
04/13/2010
Application #:
11438541
Filing Dt:
05/22/2006
Publication #:
Pub Dt:
11/22/2007
Title:
NON-VOLATILE MEMORY CELL AND METHODS THEREOF
20
Patent #:
Issue Dt:
10/21/2008
Application #:
11438890
Filing Dt:
05/23/2006
Publication #:
Pub Dt:
12/06/2007
Title:
CONTENTION-FREE HIERARCHICAL BIT LINE IN EMBEDDED MEMORY AND METHOD THEREOF
21
Patent #:
Issue Dt:
01/19/2010
Application #:
11441367
Filing Dt:
05/25/2006
Publication #:
Pub Dt:
11/29/2007
Title:
MODEL CORRESPONDENCE METHOD AND DEVICE
22
Patent #:
Issue Dt:
06/17/2008
Application #:
11441415
Filing Dt:
05/25/2006
Publication #:
Pub Dt:
11/30/2006
Title:
CHARGE PUMP CIRCUIT FOR HIGH SIDE DRIVE CIRCUIT AND DRIVER DRIVING VOLTAGE CIRCUIT
23
Patent #:
NONE
Issue Dt:
Application #:
11441869
Filing Dt:
05/26/2006
Publication #:
Pub Dt:
11/29/2007
Title:
Method of increasing coding efficiency and reducing power consumption by on-line scene change detection while encoding inter-frame
24
Patent #:
Issue Dt:
01/12/2010
Application #:
11442196
Filing Dt:
05/26/2006
Publication #:
Pub Dt:
11/29/2007
Title:
METHOD AND DEVICE FOR TESTING DELAY PATHS OF AN INTEGRATED CIRCUIT
25
Patent #:
Issue Dt:
11/06/2007
Application #:
11443198
Filing Dt:
05/30/2006
Publication #:
Pub Dt:
11/30/2006
Title:
TRANSMISSION LINE DRIVER CIRCUIT
26
Patent #:
Issue Dt:
09/22/2009
Application #:
11443199
Filing Dt:
05/30/2006
Publication #:
Pub Dt:
12/06/2007
Title:
WIRELESS RECEIVER FOR REMOVING DIRECT CURRENT OFFSET COMPONENT
27
Patent #:
Issue Dt:
08/19/2008
Application #:
11443405
Filing Dt:
05/30/2006
Publication #:
Pub Dt:
12/06/2007
Title:
DIFFERENTIAL RECEIVER CIRCUIT
28
Patent #:
Issue Dt:
10/14/2008
Application #:
11443627
Filing Dt:
05/31/2006
Publication #:
Pub Dt:
12/06/2007
Title:
DUAL SURFACE SOI BY LATERAL EPITAXIAL OVERGROWTH
29
Patent #:
Issue Dt:
06/09/2009
Application #:
11443628
Filing Dt:
05/31/2006
Publication #:
Pub Dt:
12/06/2007
Title:
TRENCH LINER FOR DSO INTEGRATION
30
Patent #:
Issue Dt:
04/21/2009
Application #:
11443971
Filing Dt:
05/31/2006
Publication #:
Pub Dt:
12/06/2007
Title:
TRANSLATIONAL PHASE LOCKED LOOP USING A QUANTIZED INTERPOLATED EDGE TIMED SYNTHESIZER
31
Patent #:
Issue Dt:
05/15/2007
Application #:
11444087
Filing Dt:
05/31/2006
Title:
SYSTEM AND METHOD FOR REDUCING CURRENT IN A DEVICE DURING TESTING
32
Patent #:
Issue Dt:
07/30/2013
Application #:
11444089
Filing Dt:
05/31/2006
Publication #:
Pub Dt:
12/06/2007
Title:
MRAM SYNTHETIC ANTIFERROMAGNET STRUCTURE
33
Patent #:
Issue Dt:
11/04/2008
Application #:
11444091
Filing Dt:
05/31/2006
Publication #:
Pub Dt:
12/06/2007
Title:
METHODS AND APPARATUS FOR RF SHIELDING IN VERTICALLY-INTEGRATED SEMICONDUCTOR DEVICES
34
Patent #:
NONE
Issue Dt:
Application #:
11444448
Filing Dt:
05/31/2006
Publication #:
Pub Dt:
12/06/2007
Title:
Method of forming semiconductor packaged device
35
Patent #:
Issue Dt:
04/29/2008
Application #:
11445652
Filing Dt:
06/02/2006
Publication #:
Pub Dt:
12/06/2007
Title:
SLEW-RATE CONTROL APPARATUS AND METHODS FOR A POWER TRANSISTOR TO REDUCE VOLTAGE TRANSIENTS DURING INDUCTIVE FLYBACK
36
Patent #:
Issue Dt:
10/02/2007
Application #:
11445657
Filing Dt:
06/02/2006
Title:
DIE LEVEL METAL DENSITY GRADIENT FOR IMPROVED FLIP CHIP PACKAGE RELIABILITY
37
Patent #:
Issue Dt:
10/01/2013
Application #:
11445981
Filing Dt:
05/31/2006
Publication #:
Pub Dt:
12/20/2007
Title:
SYSTEM AND METHOD FOR POLAR MODULATION USING POWER AMPLIFIER BIAS CONTROL
38
Patent #:
Issue Dt:
11/25/2008
Application #:
11446891
Filing Dt:
06/05/2006
Publication #:
Pub Dt:
01/03/2008
Title:
DATA COMMUNICATION FLOW CONTROL DEVICE AND METHODS THEREOF
39
Patent #:
Issue Dt:
10/06/2009
Application #:
11448225
Filing Dt:
06/07/2006
Publication #:
Pub Dt:
12/13/2007
Title:
IN-CIRCUIT VT DISTRIBUTION BIT COUNTER FOR NON-VOLATILE MEMORY DEVICES
40
Patent #:
Issue Dt:
02/22/2011
Application #:
11450070
Filing Dt:
06/09/2006
Publication #:
Pub Dt:
12/13/2007
Title:
METHODS AND APPARATUS FOR A SEMICONDUCTOR DEVICE PACKAGE WITH IMPROVED THERMAL PERFORMANCE
41
Patent #:
Issue Dt:
07/21/2009
Application #:
11450623
Filing Dt:
06/10/2006
Publication #:
Pub Dt:
12/13/2007
Title:
SWITCHING CIRCUIT AND A METHOD OF DRIVING A LOAD
42
Patent #:
Issue Dt:
07/29/2008
Application #:
11450667
Filing Dt:
06/09/2006
Publication #:
Pub Dt:
12/13/2007
Title:
METHODS AND APPARATUS FOR THERMAL MANAGEMENT IN A MULTI-LAYER EMBEDDED CHIP STRUCTURE
43
Patent #:
Issue Dt:
10/13/2009
Application #:
11452457
Filing Dt:
06/14/2006
Publication #:
Pub Dt:
12/20/2007
Title:
DC OFFSET CORRECTION FOR DIRECT CONVERSION RECEIVERS
44
Patent #:
Issue Dt:
01/01/2008
Application #:
11453200
Filing Dt:
06/15/2006
Publication #:
Pub Dt:
12/20/2007
Title:
INTEGRATOR CURRENT MATCHING
45
Patent #:
Issue Dt:
09/02/2008
Application #:
11453324
Filing Dt:
06/14/2006
Publication #:
Pub Dt:
12/20/2007
Title:
LOW PIN COUNT RESET CONFIGURATION
46
Patent #:
Issue Dt:
05/25/2010
Application #:
11453763
Filing Dt:
06/14/2006
Publication #:
Pub Dt:
12/20/2007
Title:
MICROELECTRONIC ASSEMBLY WITH BACK SIDE METALLIZATION AND METHOD FOR FORMING THE SAME
47
Patent #:
Issue Dt:
11/03/2009
Application #:
11454403
Filing Dt:
06/15/2006
Publication #:
Pub Dt:
12/20/2007
Title:
METHOD OF FORMING A BIPOLAR TRANSISTOR AND SEMICONDUCTOR COMPONENT THEREOF
48
Patent #:
Issue Dt:
12/29/2009
Application #:
11455025
Filing Dt:
06/15/2006
Publication #:
Pub Dt:
12/20/2007
Title:
INTEGRATED CMOS AND BIPOLAR DEVICES METHOD AND STRUCTURE
49
Patent #:
Issue Dt:
01/20/2009
Application #:
11457312
Filing Dt:
07/13/2006
Publication #:
Pub Dt:
01/17/2008
Title:
A DUAL MODE VOLTAGE SUPPLY CIRCUIT
50
Patent #:
Issue Dt:
01/26/2010
Application #:
11457380
Filing Dt:
07/13/2006
Publication #:
Pub Dt:
01/17/2008
Title:
A DIRECT DIGITAL SYNTHESIS CIRCUIT
51
Patent #:
Issue Dt:
08/12/2008
Application #:
11457580
Filing Dt:
07/14/2006
Publication #:
Pub Dt:
01/31/2008
Title:
COIL-LESS OVERTONE CRYSTAL OSCILLATOR
52
Patent #:
Issue Dt:
06/16/2009
Application #:
11457668
Filing Dt:
07/14/2006
Publication #:
Pub Dt:
01/17/2008
Title:
DATA LATCH WITH MINIMAL SETUP TIME AND LAUNCH DELAY
53
Patent #:
Issue Dt:
09/28/2010
Application #:
11458902
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
01/24/2008
Title:
TWISTED DUAL-SUBSTRATE ORIENTATION (DSO) SUBSTRATES
54
Patent #:
Issue Dt:
06/09/2009
Application #:
11459170
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
01/24/2008
Title:
MEMORY PIPELINING IN AN INTEGRATED CIRCUIT MEMORY DEVICE USING SHARED WORDLINES
55
Patent #:
Issue Dt:
11/04/2008
Application #:
11459837
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
01/31/2008
Title:
METHOD FOR REMOVING NANOCLUSTERS FROM SELECTED REGIONS
56
Patent #:
Issue Dt:
10/07/2008
Application #:
11459843
Filing Dt:
07/25/2006
Title:
METHOD FOR RETAINING NANOCLUSTER SIZE AND ELECTRICAL CHARACTERISTICS DURING PROCESSING
57
Patent #:
Issue Dt:
12/01/2009
Application #:
11460086
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
02/28/2008
Title:
PIPELINED DATA PROCESSOR WITH DETERMINISTIC SIGNATURE GENERATION
58
Patent #:
Issue Dt:
10/26/2010
Application #:
11460090
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
05/29/2008
Title:
DATA PROCESSING WITH RECONFIGURABLE REGISTERS
59
Patent #:
Issue Dt:
10/07/2008
Application #:
11460349
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
01/31/2008
Title:
VOLTAGE CONTROL CIRCUIT HAVING A POWER SWITCH
60
Patent #:
Issue Dt:
11/17/2009
Application #:
11460732
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/31/2008
Title:
CURRENT COMPARISON BASED VOLTAGE BIAS GENERATOR FOR ELECTRONIC DATA STORAGE DEVICES
61
Patent #:
NONE
Issue Dt:
Application #:
11460742
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/31/2008
Title:
METHOD FOR FORMING A STRESSOR LAYER
62
Patent #:
Issue Dt:
12/30/2008
Application #:
11460745
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/31/2008
Title:
MEMORY CIRCUIT USING A REFERENCE FOR SENSING
63
Patent #:
Issue Dt:
01/20/2009
Application #:
11460748
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/31/2008
Title:
TRANSFER OF STRESS TO A LAYER
64
Patent #:
Issue Dt:
09/21/2010
Application #:
11460782
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/31/2008
Title:
TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY
65
Patent #:
NONE
Issue Dt:
Application #:
11460847
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/31/2008
Title:
ESTIMATING FREQUENCY ERROR OF A SAMPLE STREAM
66
Patent #:
NONE
Issue Dt:
Application #:
11461033
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
04/10/2008
Title:
METHOD FOR PROTECTING HIGH-TOPOGRAPHY REGIONS DURING PATTERNING OF LOW-TOPOGRAPHY REGIONS
67
Patent #:
Issue Dt:
06/29/2010
Application #:
11461048
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
01/31/2008
Title:
BUS HAVING A DYNAMIC TIMING BRIDGE
68
Patent #:
Issue Dt:
05/13/2008
Application #:
11461155
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
02/21/2008
Title:
OSCILLATOR
69
Patent #:
Issue Dt:
11/06/2007
Application #:
11461200
Filing Dt:
07/31/2006
Title:
SRAM HAVING VARIABLE POWER SUPPLY AND METHOD THEREFOR
70
Patent #:
Issue Dt:
10/05/2010
Application #:
11461811
Filing Dt:
08/02/2006
Publication #:
Pub Dt:
02/28/2008
Title:
METHOD AND APPARATUS FOR RECONFIGURING A REMOTE DEVICE
71
Patent #:
NONE
Issue Dt:
Application #:
11462773
Filing Dt:
08/07/2006
Publication #:
Pub Dt:
05/29/2008
Title:
SELECTIVE STRESS RELAXATION BY AMORPHIZING IMPLANT IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT
72
Patent #:
NONE
Issue Dt:
Application #:
11464108
Filing Dt:
08/11/2006
Publication #:
Pub Dt:
02/14/2008
Title:
METHOD FOR DETERMINING BRANCH TARGET BUFFER (BTB) ALLOCATION FOR BRANCH INSTRUCTIONS
73
Patent #:
NONE
Issue Dt:
Application #:
11464112
Filing Dt:
08/11/2006
Publication #:
Pub Dt:
02/14/2008
Title:
METHOD FOR DETERMINING BRANCH TARGET BUFFER (BTB) ALLOCATION FOR BRANCH INSTRUCTIONS
74
Patent #:
Issue Dt:
02/23/2010
Application #:
11464124
Filing Dt:
08/11/2006
Publication #:
Pub Dt:
02/14/2008
Title:
MEMORY HAVING SENSE TIME OF VARIABLE DURATION
75
Patent #:
Issue Dt:
07/21/2009
Application #:
11464129
Filing Dt:
08/11/2006
Publication #:
Pub Dt:
02/14/2008
Title:
DOUBLE-RATE MEMORY
76
Patent #:
Issue Dt:
01/20/2009
Application #:
11465311
Filing Dt:
08/17/2006
Publication #:
Pub Dt:
02/21/2008
Title:
CONTROL AND TESTING OF A MICRO ELECTROMECHANICAL SWITCH
77
Patent #:
Issue Dt:
09/08/2009
Application #:
11465319
Filing Dt:
08/17/2006
Publication #:
Pub Dt:
02/21/2008
Title:
CONTROL AND TESTING OF A MICRO ELECTROMECHANICAL SWITCH HAVING A PIEZO ELEMENT
78
Patent #:
Issue Dt:
04/21/2009
Application #:
11465395
Filing Dt:
08/17/2006
Publication #:
Pub Dt:
09/06/2007
Title:
SEMICONDUCTOR OPTICAL DEVICES HAVING FIN STRUCTURES
79
Patent #:
Issue Dt:
02/24/2009
Application #:
11465402
Filing Dt:
08/17/2006
Publication #:
Pub Dt:
06/07/2007
Title:
SEMICONDUCTOR OPTICAL DEVICES AND METHOD FOR FORMING
80
Patent #:
Issue Dt:
10/07/2008
Application #:
11465843
Filing Dt:
08/21/2006
Publication #:
Pub Dt:
07/12/2007
Title:
ARRANGEMENT AND METHOD IMPEDANCE MATCHING
81
Patent #:
Issue Dt:
08/17/2010
Application #:
11465976
Filing Dt:
08/21/2006
Publication #:
Pub Dt:
02/21/2008
Title:
POWER DE-RATING REDUCTION IN A TRANSMITTER
82
Patent #:
NONE
Issue Dt:
Application #:
11466007
Filing Dt:
08/21/2006
Publication #:
Pub Dt:
02/21/2008
Title:
CHANNEL ESTIMATION USING DYNAMIC-RANGE-LIMITED PILOT SIGNALS
83
Patent #:
Issue Dt:
08/12/2008
Application #:
11467791
Filing Dt:
08/28/2006
Publication #:
Pub Dt:
03/20/2008
Title:
OVERTONE CRYSTAL OSCILLATOR AUTOMATIC CALIBRATION SYSTEM
84
Patent #:
Issue Dt:
05/29/2012
Application #:
11467988
Filing Dt:
08/29/2006
Publication #:
Pub Dt:
05/29/2008
Title:
METHOD AND APPARATUS FOR LOADING OR STORING MULTIPLE REGISTERS IN A DATA PROCESSING SYSTEM
85
Patent #:
Issue Dt:
04/21/2009
Application #:
11468458
Filing Dt:
08/30/2006
Publication #:
Pub Dt:
04/03/2008
Title:
MINIMUM MEMORY OPERATING VOLTAGE TECHNIQUE
86
Patent #:
Issue Dt:
02/24/2009
Application #:
11468521
Filing Dt:
08/30/2006
Publication #:
Pub Dt:
03/06/2008
Title:
CIRCUITRY FOR LATCHING
87
Patent #:
Issue Dt:
11/24/2009
Application #:
11468638
Filing Dt:
08/30/2006
Publication #:
Pub Dt:
03/20/2008
Title:
PROGRAMMING A MEMORY DEVICE HAVING ERROR CORRECTION LOGIC
88
Patent #:
Issue Dt:
10/28/2008
Application #:
11468815
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
03/06/2008
Title:
LEVEL SHIFTING CIRCUIT
89
Patent #:
Issue Dt:
07/15/2008
Application #:
11469074
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
03/06/2008
Title:
STORAGE CIRCUIT WITH EFFICIENT SLEEP MODE AND METHOD
90
Patent #:
Issue Dt:
11/18/2008
Application #:
11469084
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
03/06/2008
Title:
METHOD FOR POWERING AN ELECTRONIC DEVICE AND CIRCUIT
91
Patent #:
Issue Dt:
06/30/2009
Application #:
11469158
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
03/06/2008
Title:
METHOD OF FORMING CRACK ARREST FEATURES IN EMBEDDED DEVICE BUILD-UP PACKAGE AND PACKAGE THEREOF
92
Patent #:
Issue Dt:
04/28/2009
Application #:
11469163
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
05/29/2008
Title:
METHOD OF MAKING SELF-ALIGNED SPLIT GATE MEMORY CELL
93
Patent #:
NONE
Issue Dt:
Application #:
11470342
Filing Dt:
09/06/2006
Publication #:
Pub Dt:
03/06/2008
Title:
Variable switching point circuit
94
Patent #:
Issue Dt:
10/25/2011
Application #:
11470721
Filing Dt:
09/07/2006
Publication #:
Pub Dt:
04/12/2007
Title:
MULTI-THREADED PROCESSOR ARCHITECTURE
95
Patent #:
Issue Dt:
10/07/2008
Application #:
11470728
Filing Dt:
09/07/2006
Publication #:
Pub Dt:
03/15/2007
Title:
COMPUTER PROCESSOR CAPABLE OF RESPONDING WITH COMPARABLE EFFICIENCY TO BOTH SOFTWARE-STATE-INDEPENDENT AND STATE-DEPENDENT EVENTS
96
Patent #:
NONE
Issue Dt:
Application #:
11470732
Filing Dt:
09/07/2006
Publication #:
Pub Dt:
03/15/2007
Title:
Computer Processor Architecture Comprising Operand Stack and Addressable Registers
97
Patent #:
Issue Dt:
04/15/2008
Application #:
11476386
Filing Dt:
06/28/2006
Publication #:
Pub Dt:
12/28/2006
Title:
METHOD AND SYSTEM FOR REDUCING DELAY NOISE IN AN INTEGRATED CIRCUIT
98
Patent #:
Issue Dt:
11/25/2008
Application #:
11476387
Filing Dt:
06/28/2006
Publication #:
Pub Dt:
01/03/2008
Title:
STACKED LOOP ANTENNA
99
Patent #:
Issue Dt:
05/25/2010
Application #:
11476966
Filing Dt:
06/27/2006
Publication #:
Pub Dt:
12/27/2007
Title:
SYSTEM AND METHOD FOR EVM SELF-TEST
100
Patent #:
Issue Dt:
12/29/2009
Application #:
11479792
Filing Dt:
06/30/2006
Publication #:
Pub Dt:
01/03/2008
Title:
MEMS SUSPENSION AND ANCHORING DESIGN
Assignors
1
Exec Dt:
12/01/2006
2
Exec Dt:
12/01/2006
3
Exec Dt:
12/01/2006
4
Exec Dt:
12/01/2006
Assignee
1
390 GREENWICH STREET
NEW YORK, NEW YORK 10013
Correspondence name and address
CBCINNOVIS DBA FEDERAL RESEARCH
1023 FIFTEENTH STREET, NW, STE 401
ATTN: OLEH HERELIUK
WASHINGTON, DC 20005

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