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Patent #:
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Issue Dt:
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09/17/1996
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Application #:
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07963583
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Filing Dt:
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10/20/1992
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Title:
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PREFETCH/PRESTORE MECHANISM FOR PERIPHERAL CONTROLLERS WITH SHARED INTERNAL BUS
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Patent #:
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Issue Dt:
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03/24/1998
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Application #:
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07963584
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Filing Dt:
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10/20/1992
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Title:
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SCSI HOST ADAPTER WITH SHARED COMMAND AND DATA BUFFER
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Patent #:
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Issue Dt:
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08/19/1997
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Application #:
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07964532
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Filing Dt:
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10/15/1992
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Title:
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A PROGAMMABLY CONFIGURABLE HOST ADAPTER INTEGRATED CIRCUIT INCLUDING A RISC PROCESSOR
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Patent #:
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Issue Dt:
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08/06/1996
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Application #:
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08029910
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Filing Dt:
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03/11/1993
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Title:
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INTERFACE AND CONTROL CIRCUIT FOR REGULATING DATA FLOW IN A SCSI INITIATOR WITH MULTIPLE HOST BUS INTERFACE SELECTION
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Patent #:
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Issue Dt:
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05/28/1996
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Application #:
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08143363
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Filing Dt:
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10/29/1993
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Title:
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SOFTWARE CONFIGURABLE ISA BUS CARD INTERFACE WITH SECURITY ACCESS READ AND WRITE SEQUENCE TO UPPER DATA BITS AT ADDRESSES USED BY A GAME DEVICE
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Patent #:
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Issue Dt:
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05/27/1997
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Application #:
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08205002
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Filing Dt:
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03/01/1994
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Title:
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SYSTEM FOR STARTING AND COMPLETING A DATA TRANSFER FOR A SUBSEQUENTLY RECEIVED AUTOTRANSFER COMMAND AFTER RECEIVING A FIRST SCSI DATA TRANSFER COMMAND THAT IS NOT AUTOTRANSFER
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Patent #:
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Issue Dt:
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04/02/1996
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Application #:
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08205003
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Filing Dt:
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03/01/1994
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Title:
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SCSI COMMAND DESCRIPTOR BLOCK PARSING STATE MACHINE
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08229864
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Filing Dt:
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04/19/1994
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Title:
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SCSI HOST ADAPTER INTEGRATED CIRCUIT UTILIZING A SEQUENCER CIRCUIT TO CONTROL AT LEAST ONE NON-DATA SCSI PHASE WITHOUT USE OF ANY PROCESSOR
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Patent #:
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Issue Dt:
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02/06/1996
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Application #:
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08233928
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Filing Dt:
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04/28/1994
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Title:
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DYNAMIC POWER SAVING VIDEO DAC
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Patent #:
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Issue Dt:
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12/10/1996
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Application #:
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08235006
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Filing Dt:
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04/28/1994
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Title:
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ATM SWITCHING ELEMENT AND METHOD HAVING INDEPENDENTLY ACCESSIBLE CELL MEMORIES
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Patent #:
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Issue Dt:
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08/27/1996
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Application #:
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08241720
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Filing Dt:
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05/12/1994
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Title:
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ALL MOS VOLTAGE TO CURRENT CONVERTER
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Patent #:
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Issue Dt:
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12/05/1995
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Application #:
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08246722
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Filing Dt:
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05/20/1994
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Title:
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EFFICIENT DATA STORAGE ARRANGEMENT FOR FAR-END ECHO CANCELLER
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Patent #:
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Issue Dt:
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10/22/1996
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Application #:
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08250895
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Filing Dt:
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05/31/1994
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Title:
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INTEGRATED USER NETWORK INTERFACE DEVICE
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Patent #:
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Issue Dt:
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10/24/1995
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Application #:
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08251958
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Filing Dt:
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06/01/1994
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Title:
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PAIR DIVISION MULTIPLEXER FOR DIGITAL COMMUNICATIONS
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Patent #:
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Issue Dt:
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08/20/1996
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Application #:
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08251960
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Filing Dt:
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06/01/1994
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Title:
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HIGH-SPEED CMOS PSEUDO-ECL OUTPUT DRIVER
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Patent #:
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Issue Dt:
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07/16/1996
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Application #:
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08269083
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Filing Dt:
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06/30/1994
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Title:
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METHOD FOR PROTECTING AN ASIC BY RESETTING IT AFTER A PREDETERMINED TIME PERIOD
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Patent #:
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Issue Dt:
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10/08/1996
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Application #:
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08269463
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Filing Dt:
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06/30/1994
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Title:
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METHOD FOR ACCESSING A SEQUENCER CONTROL BLOCK BY A HOST ADAPTER INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/24/1997
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Application #:
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08270858
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Filing Dt:
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07/05/1994
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Title:
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GLOBAL PARITY SYMBOL FOR INTERLEAVED REED-SOLOMON CODED DATA
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Patent #:
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Issue Dt:
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07/25/1995
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Application #:
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08272837
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Filing Dt:
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07/11/1994
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Title:
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PRO-CAPTURE CIRCUIT FOR PHASE LOCKED LOOP CIRCUITS
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Patent #:
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Issue Dt:
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01/28/1997
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Application #:
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08285755
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Filing Dt:
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08/03/1994
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Title:
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ERROR FREE DATA TRANSFERS
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Patent #:
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Issue Dt:
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08/12/1997
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Application #:
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08301458
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Filing Dt:
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09/07/1994
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Title:
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STATUS INDICATOR FOR A HOST ADAPTER
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Patent #:
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Issue Dt:
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12/17/1996
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Application #:
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08341036
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Filing Dt:
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11/15/1994
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Title:
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A UNIVERSAL PROGRAMMING INTERFACE FOR CLOCK GENERATORS OPERABLE IN A PARALLEL PROGRAMMING MODE AND A SERIAL PROGRAMMING MODE
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Patent #:
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Issue Dt:
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08/20/1996
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Application #:
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08350550
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Filing Dt:
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12/07/1994
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Title:
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METHOD AND APPARATUS FOR RECOVERING A VARIABLE BIT RATE SERVICE CLOCK
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Patent #:
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Issue Dt:
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04/30/1996
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Application #:
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08352744
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Filing Dt:
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12/02/1994
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Title:
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CLOCK RECOVERY PHASE LOCKED LOOP CONTROL USING CLOCK DIFFERENCE DETECTION AND FORCED LOW FREQUENCY STARTUP
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Patent #:
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Issue Dt:
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12/23/1997
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Application #:
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08392442
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Filing Dt:
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02/22/1995
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Title:
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ERROR GENERATION CIRCUIT FOR TESTING A DIGITAL BUS
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Patent #:
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Issue Dt:
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10/29/1996
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Application #:
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08439078
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Filing Dt:
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05/11/1995
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Title:
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METHODS AND APPARATUS FOR ENQUEUEING DATA CELLS IN AN ATM SWITCH FABRIC ARCHITECTURE
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Patent #:
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Issue Dt:
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09/17/1996
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Application #:
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08439147
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Filing Dt:
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05/11/1995
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Title:
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METHODS AND APPARATUS FOR ENQUEUEING AND DEQUEUEING DATA CELLS IN AN ATM SWITCH FABRIC ARCHITECTURE
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Patent #:
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Issue Dt:
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02/25/1997
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Application #:
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08444307
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Filing Dt:
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05/18/1995
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Title:
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PROGRAMMABLE JUMP WINDOW FOR SONET COMPLIANT BIT ERROR MONITORING
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Patent #:
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Issue Dt:
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09/29/1998
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Application #:
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08461450
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Filing Dt:
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06/05/1995
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Title:
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APPROACH FOR IDENTIFYING A SUBSET OF ASYNCHRONOUS TRANSFER MODE (ATM) VPI/VCI VALUES IN THE COMPLETE VPI/VCI RANGE
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Patent #:
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Issue Dt:
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06/17/1997
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Application #:
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08462719
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Filing Dt:
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06/05/1995
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Title:
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SYSTEM FOR GENERATING SECOND INTERRUPT SIGNAL FOR DATA TRANSFER COMPLETION FOR A FIRST SCSI DATA TRANSFER COMMAND THAT IS NOT AUTOTRANSFER
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08463333
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Filing Dt:
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06/05/1995
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Title:
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SYSTEM FOR SUPPLYING INITIATOR IDENTIFICATION INFORMATION TO SCSI BUS IN A RESELECTION PHASE OF AN INITIATOR BEFORE COMPLETION OF AN AUTOTRANSFER COMMAND
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Patent #:
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Issue Dt:
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05/12/1998
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Application #:
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08463617
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Filing Dt:
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06/05/1995
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Title:
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METHOD FOR RECEIVING A FIRST SCSI COMMAND, SUBSEQUENT RECEIVING SECOND SCSI COMMAND AND STARTING DATA TRANSFER, RECONNECTING AND PERFORMING DATA TRANSFER FOR FIRST SCSI COMMAND
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Patent #:
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Issue Dt:
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02/11/1997
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Application #:
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08463649
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Filing Dt:
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06/05/1995
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Title:
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METHOD OF FLAGGING THE COMPLETION OF A SECOND COMMAND BEFORE THE COMPLETION OF A FIRST COMMAND FROM THE SAME INITIATOR IN A SCSI CONTROLLER
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08465075
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Filing Dt:
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06/05/1995
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Title:
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SYSTEM FOR STORING INITIATOR, QUEUE TAG AND LOGICAL BLOCK INFORMATION, DISCONNECTING FROM TARGET IF COMMAND IS NOT AUTO TRANSFER, RECONNECTING AND PERFORMING DATA TRANSFER
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08482529
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Filing Dt:
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06/07/1995
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Title:
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INTEGRATED CIRCUIT WITH A SERIAL PORT HAVING ONLY ONE PIN
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Patent #:
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Issue Dt:
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05/05/1998
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Application #:
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08486084
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Filing Dt:
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06/07/1995
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Title:
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A DESKEW CIRCUIT IN A HOST INTERFACE CIRCUIT
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08486096
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Filing Dt:
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06/07/1995
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|
Title:
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A METHOD OF OPERATION OF A HOST ADAPTER INTEGRATED CIRCUIT
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Patent #:
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|
Issue Dt:
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09/29/1998
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Application #:
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08503078
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Filing Dt:
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07/14/1995
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|
Title:
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METHOD AND APPARATUS FOR IMPLEMENTING AN APPLICATION PROGRAMMING INTERFACE FOR A COMMUNICATIONS BUS
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Patent #:
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|
Issue Dt:
|
06/24/1997
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Application #:
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08516215
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Filing Dt:
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08/17/1995
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|
Title:
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APPROACH TO DIRECTLY PERFORMING ASYNCHRONOUS TRANSFER MODE (ATM) ADAPTATION LAYER 5 REASSEMBLY
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Patent #:
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|
Issue Dt:
|
11/25/1997
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Application #:
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08532919
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Filing Dt:
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09/22/1995
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Title:
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PRESERVING CONFIGURATION INFORMATION IN A SCAM BASED SCSI SYSTEM
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Patent #:
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|
Issue Dt:
|
06/17/1997
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Application #:
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08551530
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Filing Dt:
|
11/01/1995
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|
Title:
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STATE MACHINE ARCHITECTURE FOR CONCURRENT PROCESSING OF MULTIPLEXED DATA STREAMS
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Patent #:
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|
Issue Dt:
|
09/15/1998
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Application #:
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08552771
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Filing Dt:
|
11/03/1995
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|
Title:
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SPLIT VIDEO ARCHITECTURE FOR PERSONAL COMPUTERS
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|
|
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Patent #:
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|
Issue Dt:
|
05/12/1998
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Application #:
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08568347
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Filing Dt:
|
12/06/1995
|
|
Title:
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ALLOWED CELL RATE RECIPROCAL APPROXIMATION IN RATE-BASED AVAILABLE BIT RATE SCHEDULERS
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Patent #:
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|
Issue Dt:
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09/16/1997
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Application #:
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08568379
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Filing Dt:
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12/06/1995
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Title:
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TRAFFIC CONTROLLER FOR CELL-BASED TRANSMISSION
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Patent #:
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|
Issue Dt:
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10/14/1997
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Application #:
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08574922
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Filing Dt:
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12/19/1995
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Title:
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RING OSCILLATOR HAVING A SUBSTANTIALLY SINUSOIDAL SIGNAL
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08581901
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Filing Dt:
|
01/02/1996
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|
Title:
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CMOS SONET/ATM RECEIVER SUITABLE FOR USE WITH PSEUDO ECL AND TTL SIGNALING ENVIROMENTS
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Patent #:
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|
Issue Dt:
|
10/07/1997
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Application #:
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08582881
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Filing Dt:
|
01/04/1996
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|
Title:
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SINGLE PIN CRYSTAL OSCILLATOR CIRCUIT
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Patent #:
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|
Issue Dt:
|
07/06/1999
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Application #:
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08592800
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Filing Dt:
|
01/26/1996
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|
Title:
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A SERIAL PORT HAVING ONLY A SINGLE TERMINAL FOR INFORMATION TRANSFER TO AND FROM AN INTEGRATED CIRCUIT
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Patent #:
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|
Issue Dt:
|
12/15/1998
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Application #:
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08615476
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Filing Dt:
|
03/15/1996
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Title:
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METHOD FOR SPECIFYING CONCURRENT EXECUTION OF A STRING OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE
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Patent #:
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|
Issue Dt:
|
03/09/1999
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Application #:
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08615477
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Filing Dt:
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03/15/1996
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|
Title:
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HOST ADAPTER SYSTEM INCLUDING AN INTEGRATED PCI BUFFER CONTROLLER AND XOR FUNCTION CIRCUIT
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Patent #:
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Issue Dt:
|
02/02/1999
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Application #:
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08615478
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Filing Dt:
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03/15/1996
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Title:
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HARDWARE METHOD FOR VERIFYING THAT AN AREA OF MEMORY HAS ONLY ZERO VALUES
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Patent #:
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|
Issue Dt:
|
04/06/1999
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Application #:
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08615479
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Filing Dt:
|
03/15/1996
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|
Title:
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METHOD FOR CONCURRENTLY EXECUTING A CONFIGURED STRING OF CONCURRENT I/O COMMAND BLOCKS WITHIN A CHAIN CONCURRENTLY TO PERFORM A RAID 5 I/O OPERATION
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Patent #:
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Issue Dt:
|
10/20/1998
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Application #:
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08615883
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Filing Dt:
|
03/04/1996
|
|
Title:
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POWER SUPPLY SELF-ADJUSTED CIRCUIT FOR DUAL OR MULTIPLE VOLTAGE INTEGRATED CIRCUITS
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|
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Patent #:
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|
Issue Dt:
|
06/16/1998
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Application #:
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08616817
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Filing Dt:
|
03/15/1996
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|
Title:
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CHAIN MANAGER FOR USE IN EXECUTING A CHAIN OF I/O COMMAND BLOCKS
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|
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Patent #:
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|
Issue Dt:
|
08/18/1998
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Application #:
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08616836
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Filing Dt:
|
03/15/1996
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|
Title:
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METHOD FOR SPECIFYING EXECUTION OF ONLY ONE OF A PAIR OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/26/1998
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Application #:
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08616838
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Filing Dt:
|
03/15/1996
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|
Title:
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METHOD FOR ENHANCING PERFORMANCE OF A RAID 1 READ OPERATION USING A PAIR OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
09/22/1998
|
Application #:
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08616846
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Filing Dt:
|
03/15/1996
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|
Title:
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I/O COMMAND BLOCK CHAIN STRUCTURE IN A MEMORY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
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08616875
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
ASYNCHRONOUS BIT-TABLE CALENDAR FOR ATM SWITCH
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08617990
|
Filing Dt:
|
03/15/1996
|
|
Title:
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METHOD FOR SEQUENCING EXECUTION OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE BY SETTING HOLD-OFF FLAGS AND CONFIGURING A COUNTER IN EACH I/O COMMAND BLOCK
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|
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Patent #:
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|
Issue Dt:
|
11/23/1999
|
Application #:
|
08617991
|
Filing Dt:
|
03/15/1996
|
|
Title:
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A METHOD OF ENABLING AND DISABLING A DATA FUNCTION IN AN INTEGRATED CIRCUIT
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Patent #:
|
|
Issue Dt:
|
01/06/1998
|
Application #:
|
08622398
|
Filing Dt:
|
03/27/1996
|
|
Title:
|
AVAILABLE BIT RATE SCHEDULER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/1998
|
Application #:
|
08648710
|
Filing Dt:
|
05/16/1996
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|
Title:
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METHOD AND APPARATUS FOR RECOVERY OF PEAK CELL RATE TOKENS IN AN ATM NETWORK INTERFACE
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Patent #:
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Issue Dt:
|
03/31/1998
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Application #:
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08650836
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Filing Dt:
|
05/20/1996
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Title:
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LOW VOLTAGE SILICON COTROLLED RECTIFIER STRUCTURE FOR ESD INPUT PAD PROTECTION IN CMOS IC'S
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Patent #:
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Issue Dt:
|
06/02/1998
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Application #:
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08664119
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Filing Dt:
|
06/14/1996
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Title:
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PROCESS COMPENSATED INTEGRATED CIRCUIT OUTPUT DRIVER
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Patent #:
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Issue Dt:
|
04/28/1998
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Application #:
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08666087
|
Filing Dt:
|
06/19/1996
|
|
Title:
|
VARIABLE BIT RATE SCHEDULER
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Patent #:
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Issue Dt:
|
04/21/1998
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Application #:
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08666088
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Filing Dt:
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06/19/1996
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Title:
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COMBINATION LOCAL ATM SEGMENTATION AND REASSEMBLY AND PHYSICAL LAYER DEVICE
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Patent #:
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Issue Dt:
|
11/21/2000
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Application #:
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08680869
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Filing Dt:
|
07/16/1996
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|
Title:
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ATM ARCHITECTURE AND SWITCHING ELEMENT
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|
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Patent #:
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Issue Dt:
|
02/16/1999
|
Application #:
|
08687009
|
Filing Dt:
|
07/16/1996
|
|
Title:
|
GLOBAL PARITY SYMBOL FOR INTERLEAVED REED-SOLOMON CODED DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
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Application #:
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08797802
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Filing Dt:
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02/07/1997
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Title:
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ERROR GENERATION CIRCUIT FOR TESTING A DIGITAL BUS
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08808526
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Filing Dt:
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02/28/1997
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Title:
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INTERLEAVED BURST XOR USING A SINGLE MEMORY POINTER
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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08829044
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Filing Dt:
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03/31/1997
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Title:
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SHIFT REGISTER-BASED XOR ACCUMULATOR ENGINE FOR GENERATING PARITY IN A DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
|
07/04/2000
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Application #:
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08829432
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Filing Dt:
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03/31/1997
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Title:
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WRITE SYNCHRONIZATION SYSTEM ON A HEADERLESS FORMAT MAGNETIC DISK DEVICE
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Patent #:
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Issue Dt:
|
12/14/1999
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Application #:
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08866427
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Filing Dt:
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05/30/1997
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Title:
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METHODS AND APPARATUSES FOR AUTOMATIC BANK SWITCHING IN A HOST ADAPTER MEMORY
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Patent #:
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Issue Dt:
|
01/04/2000
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Application #:
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08872019
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Filing Dt:
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06/10/1997
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Title:
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EXTERNAL I/O CONTROLLER SYSTEM FOR AN INDEPENDENT ACCESS PARITY DISK ARRAY
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Patent #:
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Issue Dt:
|
12/21/1999
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Application #:
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08874817
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Filing Dt:
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06/13/1997
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Title:
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PROGRAMMABLE LOGIC DATAPATH THAT MAY BE USED IN A FIELD PROGRAMMABLE DEVICE
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Patent #:
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Issue Dt:
|
11/02/1999
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Application #:
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08876539
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Filing Dt:
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06/09/1997
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Title:
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STATUS INDICATOR FOR A HOST ADAPTER
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Patent #:
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Issue Dt:
|
05/09/2000
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Application #:
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08882170
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Filing Dt:
|
06/25/1997
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Title:
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FULL ENCLOSURE CHASSIS SYSTEM WITH TOOL-FREE ACCESS TO HOT-PLUGGABLE CIRCUIT BOARDS THEREIN
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|
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Patent #:
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|
Issue Dt:
|
08/29/2000
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Application #:
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08887349
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Filing Dt:
|
07/02/1997
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|
Title:
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HIGH-SPEED SERIAL DATA CABLE WITH IMPROVED ELECTROMAGNETIC PERFORMANCE
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|
|
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Patent #:
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|
Issue Dt:
|
08/03/1999
|
Application #:
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08906369
|
Filing Dt:
|
08/05/1997
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|
Title:
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COMMAND INTERPRETER SYSTEM IN AN I/O CONTROLLER
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|
|
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Patent #:
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|
Issue Dt:
|
05/18/1999
|
Application #:
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08906765
|
Filing Dt:
|
08/05/1997
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|
Title:
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SYSTEM FOR COPYING IOBS FROM FIFO INTO I/O ADAPTER, WRITING DATA COMPLETED IOB, AND INVALIDATING COMPLETED IOB IN FIFO FOR REUSE OF FIFO
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|
|
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Patent #:
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|
Issue Dt:
|
05/16/2000
|
Application #:
|
08923810
|
Filing Dt:
|
09/04/1997
|
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Title:
|
METHOD OF FORMING A HIGH-PRECISION LINEAR MOS CAPACIOTR USING CONVENTIONAL MOS DEVICE PROCESSING STEPS
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|
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Patent #:
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Issue Dt:
|
02/08/2000
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Application #:
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08926303
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Filing Dt:
|
09/05/1997
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Title:
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METHOD AND APPARATUS FOR DETERMINING SECTOR ADDRESSES FROM MEDIA HAVING DATA WRITTEN IN A HEADERLESS FORMAT
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|
|
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Patent #:
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|
Issue Dt:
|
08/14/2001
|
Application #:
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08937285
|
Filing Dt:
|
09/15/1997
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|
Title:
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METHOD AND APPARATUS TO IDENTIFY FLOWS IN DATA SYSTEMS
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|
|
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Patent #:
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|
Issue Dt:
|
05/21/2002
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Application #:
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08938828
|
Filing Dt:
|
09/29/1997
|
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Title:
|
APPARATUS AND METHOD FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS CONNECTED TO EACH OTHER BY A SINGLE LINE
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|
|
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Patent #:
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Issue Dt:
|
06/29/1999
|
Application #:
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08941347
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Filing Dt:
|
09/30/1997
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|
Title:
|
THREE-STATE PHASE-DECTECTOR/CHARGE PUMP IWTH NO DEAD-BAND OFFERING TUNABLE PHASE IN PHASE-LOCKED CIRCUITS
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|
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Patent #:
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Issue Dt:
|
10/26/1999
|
Application #:
|
08942373
|
Filing Dt:
|
10/02/1997
|
|
Title:
|
INTEGRATED PCI BUFFER CONTROLLER AND XOR FUNCTION CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
10/26/1999
|
Application #:
|
08953766
|
Filing Dt:
|
10/17/1997
|
|
Title:
|
RECONFIGURABLE ARITHMETIC DATAPATH
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/18/2000
|
Application #:
|
08963345
|
Filing Dt:
|
11/03/1997
|
|
Title:
|
DATAPATH CONTROL LOGIC FOR PROCESSORS HAVING INSTRUCTION SET ARCHITECTURES IMPLEMENTED WITH HIERARCHICALLY ORGANIZED PRIMITIVE OPERATIONS
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|
|
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|
Patent #:
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|
Issue Dt:
|
07/13/1999
|
Application #:
|
08963346
|
Filing Dt:
|
11/03/1997
|
|
Title:
|
ADAPTABLE INPUT/OUTPUT PIN CONTROL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/17/1999
|
Application #:
|
08963387
|
Filing Dt:
|
11/03/1997
|
|
Title:
|
PROCESSOR HAVING AN INSTRUCTION SET ARCHITECTURE IMPLEMENTED WITH HIERARCHICALLY ORGANIZED PRIMITIVE OPERATIONS
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|
|
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Patent #:
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|
Issue Dt:
|
01/23/2001
|
Application #:
|
08963391
|
Filing Dt:
|
11/03/1997
|
|
Title:
|
VIRTUAL REGISTER SETS
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/09/2000
|
Application #:
|
08963754
|
Filing Dt:
|
11/04/1997
|
|
Title:
|
SYSTEM AND METHOD FOR REAL-TIME DATA BACKUP USING SNAPSHOT COPYING WITH SELECTIVE CAMPACTION OF BACKUP DATA
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08963902
|
Filing Dt:
|
11/04/1997
|
|
Title:
|
FILE ARRAY COMMUNICATIONS INTERFACE FOR COMMUNICATING BETWEEN A HOST COMPUTER AND AN ADAPTER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
08964304
|
Filing Dt:
|
11/04/1997
|
|
Title:
|
FILE ARRAY STORAGE ARCHITECTURE HAVING FILE SYSTEM DISTRIBUTED ACROSS A DATA PROCESSING PLATFORM
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/14/2000
|
Application #:
|
08965737
|
Filing Dt:
|
11/07/1997
|
|
Title:
|
MECHANISM TO SUPPORT AN UTOPIA INTERFACE OVER A BACKPLANE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/17/2000
|
Application #:
|
08970882
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
MANY DIMENSIONAL CONGESTION DETECTION SYSTEM AND METHOD
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/11/2000
|
Application #:
|
08988016
|
Filing Dt:
|
12/10/1997
|
|
Title:
|
COMMAND QUEUING SYSTEM FOR A HARDWARE ACCELERATED COMMAND INTERPRETER ENGINE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
08988940
|
Filing Dt:
|
12/11/1997
|
|
Title:
|
METHOD AND APPARATUS FOR HIGH-SPEED, SCALABLE COMMUNICATION SYSTEM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
09012267
|
Filing Dt:
|
01/23/1998
|
|
Title:
|
DECENTRALIZED FILE MAPPING IN A STRIPED NETWORK FILE SYSTEM IN A DISTRIBUTED COMPUTING ENVIRONMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09016764
|
Filing Dt:
|
01/30/1998
|
|
Title:
|
METHOD FOR SELECTIVELY BOOTING FROM A DESIRED PERIPHERAL DEVICE
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|
