Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 052243/0131 | |
| Pages: | 6 |
| | Recorded: | 03/27/2020 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10319119
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Filing Dt:
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12/13/2002
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Title:
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SEMICONDUCTOR-ON-INSULATOR CHIP INCORPORATING PARTIALLY-DEPLETED, FULLY-DEPLETED, AND MULTIPLE-GATE DEVICES
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10919328
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Filing Dt:
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08/17/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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METHOD FOR MANUFACTURING DUAL DAMASCENE STRUCTURE WITH A TRENCH FORMED FIRST
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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11114567
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Filing Dt:
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04/25/2005
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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PROFILE CONFINEMENT TO IMPROVE TRANSISTOR PERFORMANCE
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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11212739
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Filing Dt:
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08/29/2005
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Publication #:
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Pub Dt:
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03/01/2007
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Title:
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VERTICAL FLASH MEMORY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11401308
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Filing Dt:
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04/11/2006
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Publication #:
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Pub Dt:
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08/31/2006
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Title:
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Method for manufacturing dual damascene structure with a trench formed first
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Patent #:
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Issue Dt:
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02/24/2009
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Application #:
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11716104
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Filing Dt:
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03/09/2007
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Publication #:
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Pub Dt:
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09/11/2008
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Title:
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DESIGN TECHNIQUES FOR STACKING IDENTICAL MEMORY DIES
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Assignee
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| 8105 RASOR BLVD SUITE 210 |
| PLANO, TEXAS 75024-0116 |
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Correspondence name and address
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TRENCHANT BLADE TECHNOLOGIES LLC
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8105 RASOR BLVD SUITE 210
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PLANO, TX 75024-0116
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