Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 040417/0141 | |
| Pages: | 5 |
| | Recorded: | 10/19/2016 | | |
| Attorney Dkt #: | MEIGI-MEI2PC161019 |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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10024721
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Filing Dt:
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12/21/2001
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Publication #:
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Pub Dt:
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06/27/2002
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Title:
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SEMICONDUCTOR CHIP, SET OF SEMICONDUCTOR CHIPS AND MULTICHIP MODULE
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10097140
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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10/17/2002
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Title:
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SEMICONDUCTOR CHIP AND MULTI-CHIP MODULE
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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11068807
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Filing Dt:
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03/02/2005
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Publication #:
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Pub Dt:
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09/08/2005
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Title:
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SEMICONDUCTOR DEVICE FOR REDUCING PARASITIC CAPACITANCE PRODUCED IN THE VICINITY OF A TRANSISTOR LOCATED WITHIN THE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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11073738
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Filing Dt:
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03/08/2005
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Publication #:
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Pub Dt:
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09/15/2005
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11377452
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Filing Dt:
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03/17/2006
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Publication #:
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Pub Dt:
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12/21/2006
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Title:
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METHOD FOR FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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Assignee
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| 1006, OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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Correspondence name and address
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PANASONIC CORPORATION
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2-1-61, SHIROMI, CHUO-KU
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7F OBP PANASONIC TOWER
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OSAKA, 540-6207 JAPAN
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