Total properties:
185
Page
1
of
2
Pages:
1 2
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08599075
|
Filing Dt:
|
02/09/1996
|
|
Title:
|
HIDDEN PRECHARGE PSEUDO CACHE DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08681718
|
Filing Dt:
|
07/29/1996
|
|
Title:
|
METHOD AND APPARATUS FOR PREVENTING PARTICLE CONTAMINATION IN A PROCESS CHAMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08953609
|
Filing Dt:
|
10/17/1997
|
|
Title:
|
MOSFET WITH SELF-ALIGNED SILICIDATION AND GATE-SIDE AIR-GAP STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08954412
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
METHOD FOR FORMING A DRAM CELL WITH A DOUBLE-CROWN SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08954413
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
METHOD FOR FORMING A DRAM CELL WITH A MULTIPLE PILLAR-SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08954416
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
METHOD OF MAKING DEEP SUB-MICRON METER MOSFET WITH A HIGH PERMITIVITY GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08958536
|
Filing Dt:
|
10/27/1997
|
|
Title:
|
METHOD FOR FORMING A DRAM CELL WITH A FORK-SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08960870
|
Filing Dt:
|
10/31/1997
|
|
Title:
|
DOUBLE STAIR-LIKE CAPACITOR STRUCTURE FOR A DRAM CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
08962003
|
Filing Dt:
|
10/31/1997
|
|
Title:
|
DRAM CELL WITH A RUGGED STACKED TRENCH (RST) CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08962623
|
Filing Dt:
|
11/03/1997
|
|
Title:
|
METHOD FOR FORMING A DRAM CELL WITH A RAGGED POLYSILICON CROWN-SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/1998
|
Application #:
|
08962625
|
Filing Dt:
|
11/03/1997
|
|
Title:
|
METHOD OF MAKING A DOUBLE STAIR-LIKE CAPACITOR FOR A HIGH DENSITY DRAM CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
08984871
|
Filing Dt:
|
12/04/1997
|
|
Title:
|
SELF-ALIGNED SILICIDED MOSFETS WITH A GRADED S/D JUNCTION AND GATE-SIDE AIR-GAP STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08988031
|
Filing Dt:
|
12/10/1997
|
|
Title:
|
METHOFOR A RING-LIKE CAPACITOR IN A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08988034
|
Filing Dt:
|
12/10/1997
|
|
Title:
|
METHOD FOR FORMING SHALLOW TRENCH ISOLATION WITH GLOBAL PLANARIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08988035
|
Filing Dt:
|
12/10/1997
|
|
Title:
|
METHOD OF FORMING A T-GATE LIGHTLY-DOPED DRAIN SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
08988518
|
Filing Dt:
|
12/10/1997
|
|
Title:
|
CIRCUIT OF REDUCING TRANSMISSION DELAY FOR SYNCHRONOUS DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08990117
|
Filing Dt:
|
12/12/1997
|
|
Title:
|
METHOD OF MANUFACTURING TRENCH DRAM CELLS WITH SELF-ALIGNED FIELD PLATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
08990167
|
Filing Dt:
|
12/12/1997
|
|
Title:
|
SELF-ALIGNED SILICIDED MOS TRANSISTOR WITH A LIGHTLY DOPED DRAIN BALLAST RESISTOR FOR ESD PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08994053
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
METHOD OF MAKING ULTRA-SHORT CHANNEL MOSFET WITH SELF-ALIGNED SILICIDED CONTACT AND EXTENDED S/D JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
08994178
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
METHOD OF FORMING A SELF-ALIGNED SILICIDE MOSFET WITH AN EXTENDED ULTRA-SHALLOW S/D JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08995569
|
Filing Dt:
|
12/22/1997
|
|
Title:
|
METHOD OF MAKING A MULTIPLE MUSHROOM SHAPE CAPACITOR FOR HIGH DENSITY DRAMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
08996694
|
Filing Dt:
|
12/23/1997
|
|
Title:
|
METHOD OF MAKING SELF-ALIGNED SILICIDED MOS TRANSISTOR WITH ESD PROTECTION IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08998796
|
Filing Dt:
|
12/29/1997
|
|
Title:
|
METHOD OF MAKING MOS TRANSISTORS WITH A GATE-SIDE AIR-GAP STRUCTURE AND AN EXTENSION ULTRA-SHALLOW S/D JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
08998933
|
Filing Dt:
|
12/29/1997
|
|
Title:
|
METHOD OF FABRICATING DRAM CELL WITH CAPACITOR HAVING MULTIPLE CONCAVE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08999268
|
Filing Dt:
|
12/29/1997
|
|
Title:
|
METHOD TO FORM STACKED-SI GATE PMOSFETS WITH ELEVATED AND EXTENDED S/D JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
08999449
|
Filing Dt:
|
12/29/1997
|
|
Title:
|
DRAM CELL WITH A MULTIPLE MUSHROOM-SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09001978
|
Filing Dt:
|
12/31/1997
|
|
Title:
|
METHOD OF FABRICATING CMOS TRANSISTORS WITH A PLANAR SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09002607
|
Filing Dt:
|
01/05/1998
|
|
Title:
|
METHOD TO FORM HIGH DENSITY NAND STRUCTURE NONVOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09002608
|
Filing Dt:
|
01/05/1998
|
|
Title:
|
METHOD OF FORMING MOSFETS WITH RECESSED SELF-ALIGNED SILICIDE GRADUAL S/D JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
09004448
|
Filing Dt:
|
01/08/1998
|
|
Title:
|
AN ULTRA-SHORT CHANNEL RECESSED GATE MOSFET WITH A BURIED CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
09004449
|
Filing Dt:
|
01/08/1998
|
|
Title:
|
PROCESS TO FABRICATE ULTRA-SHORT CHANNEL NMOSFETS WITH SELF-ALIGNED SILICIDE CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09013424
|
Filing Dt:
|
01/16/1998
|
|
Title:
|
DISCHARGE LAMP FOR AN AUTOMOTIVE VEHICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09013425
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
METHOD TO FORM DIFFERENT THRESHOLD NMOSFETS FOR READ ONLY MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
09013429
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
METHOD TO FORM ELEVATED SOURCE/DRAIN WITH SOLID PHASE DIFFUSED SOURCE/DRAIN EXTENSION FOR MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09013676
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
REDUCED MASK CMOS SALICIDED PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
09013682
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH AN INVERSE-T GATE LIGHTLY-DOPED DRAIN STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09013689
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
METHOD OF FORMING A TRENCH CAPACITOR FOR A DRAM CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
09013690
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
DRAM CELL WITH A FORK-SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
09013691
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
METHOD FOR FORMING A SEMICODUCTOR DEVICE WITH A GRADED LIGHTLY-DOPED DRAIN STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09013694
|
Filing Dt:
|
01/26/1998
|
|
Title:
|
PROCESS TO FORM CMOS DEVICES WITH HIGHER ESD AND HOT CARRIER IMMUNITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
09014862
|
Filing Dt:
|
01/28/1998
|
|
Title:
|
METHOD TO FORM A RAGGED POLY-SI STRUCTURE FOR HIGH DENSITY DRAM CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09014864
|
Filing Dt:
|
01/28/1998
|
|
Title:
|
METHOD TO SIMULATANEOUSLY FABRICATE THE SELF-ALIGNED SILICIDED DEVICES AND ESD PROTECTIVE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09014865
|
Filing Dt:
|
01/28/1998
|
|
Title:
|
CMOS PROCESS FOR FORMING PLANARIZED TWIN WELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09014866
|
Filing Dt:
|
01/28/1998
|
|
Title:
|
METHOD FOR FORMING A STRESS-FREE SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
09014867
|
Filing Dt:
|
01/28/1998
|
|
Title:
|
ULTRA-SHORT CHANNEL RECESSED GATE MOSFET WITH A BURIED CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09014868
|
Filing Dt:
|
01/28/1998
|
|
Title:
|
STRESS-FREE SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09020229
|
Filing Dt:
|
02/06/1998
|
|
Title:
|
METHOD TO FABRICATE DEEP SUB-UM CMOSFETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09020230
|
Filing Dt:
|
02/06/1998
|
|
Title:
|
HIGH DENSITY NAND STRUCTURE NONVOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09023260
|
Filing Dt:
|
02/13/1998
|
|
Title:
|
DUAL DAMASCENE MULTI-LEVEL METALLIZATION AND INTERCONNECTION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09023261
|
Filing Dt:
|
02/13/1998
|
|
Title:
|
DUAL DAMASCENE PROCESS FOR MULTI-LEVEL METALLIZATION AND INTERCONNECTION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
09023453
|
Filing Dt:
|
02/13/1998
|
|
Title:
|
METHOD TO FORM A CAPACITOR FOR HIGH DENSITY DRAM CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09023454
|
Filing Dt:
|
02/13/1998
|
|
Title:
|
MOSFETS WITH RECESSED SELF-ALIGNED SILICIDE GRADUAL S/D JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
09024772
|
Filing Dt:
|
02/17/1998
|
|
Title:
|
METHOD TO FABRICATE SHORT-CHANNEL MOSFETS WITH AN IMPROVEMENT IN ESD RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09025969
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
MOSFETS WITH A RECESSED SELF-ALIGNED SILICIDE CONTACT AND AN EXTENDED SOURCE/DRAIN JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
09025970
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
DRAM CELL WITH A DOUBLE-CROWN SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09025971
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
METHOD FOR FORMING SELF-ALIGNED SILICIDED MOS TRANSISTORS WITH ASYMMETRIC ESD PROTECTING TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09032008
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHOD TO MANUFACTURE NONVOLATILE MEMORIES WITH A TRENCH-PILLAR CELL STRUCTURE FOR HIGH CAPACITIVE COUPLING RATIO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09033526
|
Filing Dt:
|
03/02/1998
|
|
Title:
|
ELEVATED SOURCE/DRAIN MOSFET WITH SOLID PHASE DIFFUSED SOURCE/DRAIN EXTENSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
09033527
|
Filing Dt:
|
03/02/1998
|
|
Title:
|
METHOD OF MAKING NANOMETER SI ISLANDS FOR SINGLE ELECTRON TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09033546
|
Filing Dt:
|
03/02/1998
|
|
Title:
|
HIGH DENSITY AND LOW POWER FLASH MEMORIES WITH A HIGH CAPACITIVE-COUPLING RATIO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09033560
|
Filing Dt:
|
03/02/1998
|
|
Title:
|
METHOD OF MAKING SINGLE-ELECTRON-TUNNELING CMOS TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09033948
|
Filing Dt:
|
03/02/1998
|
|
Title:
|
METHOD TO FORM ULTRA-SHORT CHANNEL MOSFET WITH A GATE-SIDE AIRGAP STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
09034635
|
Filing Dt:
|
03/04/1998
|
|
Title:
|
METHOD FOR FORMING AN ISOLATION REGION IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
09036027
|
Filing Dt:
|
03/06/1998
|
|
Title:
|
METHOD OF FORMING HIGH CAPACITIVE-COUPLING RATIO AND HIGH SPEED FLASH MEMORIES WITH A TEXTURED TUNNEL OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
09042347
|
Filing Dt:
|
03/13/1998
|
|
Title:
|
METHOD FOR FORMING HIGH DENSITY NONVOLATILE MEMORIES WITH HIGH CAPACITIVE-COUPLING RATIO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
09042348
|
Filing Dt:
|
03/13/1998
|
|
Title:
|
METHOD TO FORM ULTRA-SHORT CHANNEL ELEVATED S/D MOSFETS ON AN ULTRA-THIN SOI SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09042349
|
Filing Dt:
|
03/13/1998
|
|
Title:
|
METHOD TO FORM GLOBAL PLANARIZED SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
09042351
|
Filing Dt:
|
03/13/1998
|
|
Title:
|
LOW MASK COUNT SELF-ALIGNED SILICIDED CMOS TRANSISTORS WITH A HIGH ELECTROSTATIC DISCHARGE RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09042352
|
Filing Dt:
|
03/13/1998
|
|
Title:
|
METHOD TO FABRICATE DUAL THRESHOLD CMOS CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
09046331
|
Filing Dt:
|
03/23/1998
|
|
Title:
|
3-D CMOS TRANSISTORS WITH HIGH ESD RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09046332
|
Filing Dt:
|
03/23/1998
|
|
Title:
|
BLANKET WELL COUNTER DOPING PROCESS FOR HIGH SPEED/LOW POWER MOSFETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09046343
|
Filing Dt:
|
03/23/1998
|
|
Title:
|
HIGH DENSITY/SPEED NONVOLATILE MEMORIES WITH A TEXTURED TUNNEL OXIDE AND A HIGH CAPACITIVE-COUPLING RATIO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
09048154
|
Filing Dt:
|
03/25/1998
|
|
Title:
|
METHOD OF FORMING DEEP SUB-MICRON CMOS TRANSISTORS WITH SELF-ALIGNED SILICIDED CONTACT AND EXTENDED S/D JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09048549
|
Filing Dt:
|
03/25/1998
|
|
Title:
|
METHOD FOR FORMING A HIGH DENSITY SHALLOW TRENCH CONTACTLESS NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09050540
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
HIGH DENSITY SHALLOW TRENCH CONTACTLESS NONVOLITILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
09050541
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
METHOD OF MAKING SELF-ALIGNED SILICIDE CMOS TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
09050668
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
MOSFETS STRUCTURE WITH A RECESSED SELF-ALIGNED SILICIDE CONTACT AND AN EXTENDED SOURCE/DRAIN JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
09050669
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH AN INVERSE-T GATE LIGHTLY-DOPED DRAIN STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09050670
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
ULTRA-SHORT CHANNEL NMOSFETS WITH SELF-ALIGNED SILICIDE CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
09052280
|
Filing Dt:
|
03/31/1998
|
|
Title:
|
CMOS TRANSISTORS WITH SELF-ALIGNED PLANARIZATION TWIN-WELL BY USING FEWER MASK COUNTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
09054128
|
Filing Dt:
|
04/02/1998
|
|
Title:
|
METHOD FOR MANUFACTURING A CAPACITOR OF A TRENCH DTAM CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09056222
|
Filing Dt:
|
04/07/1998
|
|
Title:
|
METHOD TO SIMULTANEOUSLY FABRICATE THE SELF-ALIGNED SILICIDED DEVICES AND ESD PROTECTION DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09057866
|
Filing Dt:
|
04/09/1998
|
|
Title:
|
PROCESS TO FABRICATE THE NON-SILICIDE REGION FOR ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09057867
|
Filing Dt:
|
04/09/1998
|
|
Title:
|
LOW MASK COUNT PROCESS TO FABRICATE MASK READ ONLY MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09057869
|
Filing Dt:
|
04/09/1998
|
|
Title:
|
SINGLE ELECTRON TRANSISTOR MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09060565
|
Filing Dt:
|
04/14/1998
|
|
Title:
|
STACKED CAPACITOR STRUCTURE FOR HIGH DENSITY DRAM CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
09060566
|
Filing Dt:
|
04/14/1998
|
|
Title:
|
MANUFACTURING METHOD FOR MASK ROM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09062827
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
3-D CMOS TRANSISTORS WITH HIGH ESD RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09062829
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
SELF-ALIGNED SILICIDED MOS DEVICES WITH AN EXTENDED S/D JUNCTION AND AN ESD PROTECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09063210
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
SHALLOW TRENCH ISOLATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
09063211
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
DOUBLE CODING PROCESSES FOR MASK READ ONLY MEMORY (ROM) DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09064261
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
PROCESS TO FABRICATE PLANARIZED DEEP-SHALLOW TRENCH ISOLATION HAVING U PPER AND LOWER PORTIONS WITH OXIDIZED SEMICONDUCTOR TRENCH FILL IN THE UPPER PORTION AND SEMICONDUCTOR TRENCH FILL IN THE LOWER PORTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/1999
|
Application #:
|
09064262
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
METHOD TO FORM MOSFET WITH AN INVERSE T-SHAPED AIR-GAP GATE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09064430
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
METHOD OF ELIMINATING BURIED CONTACT TRENCH IN SRAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09064976
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
PLANARIZED DEEP-SHALLOW TRENCH ISOLATION FOR CMOS/BIPOLAR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09065323
|
Filing Dt:
|
04/23/1998
|
|
Title:
|
TRENCH-FREE BURIED CONTACT FOR SRAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09065472
|
Filing Dt:
|
04/23/1998
|
|
Title:
|
ULTRA-SHORT CHANNEL ELEVATED S/D MOSFETS FORMED ON AN ULTRA-THIN SOI SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2001
|
Application #:
|
09072289
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
FIPOS METHOD OF FORMING SOI CMOS STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09072290
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
METHOD TO FORM SHALLOW TRENCH ISOLATION WITH AN OXYNITRIDE BUFFER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09072291
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
DOUBLE CODING MASK READ ONLY MEMORY (MASK ROM) FOR MINIMIZING BAND-TO-BAND LEAKAGE
|
|
