Total properties:
64
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Patent #:
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Issue Dt:
|
10/08/1991
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Application #:
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07524183
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Filing Dt:
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05/15/1990
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Title:
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BASIC CELL FOR BICMOS GATE ARRAY
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Patent #:
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Issue Dt:
|
11/26/1991
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Application #:
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07524207
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Filing Dt:
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05/15/1990
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Title:
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BICMOS LOGIC CIRCUIT FOR ASIC APPLICATIONS
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Patent #:
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Issue Dt:
|
02/22/1994
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Application #:
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07717140
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Filing Dt:
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06/18/1991
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Title:
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BASIC CELL ARCHITECTURE FOR MASK PROGRAMMABLE GATE ARRAY WITH 3 OR MORE SIZE TRANSISTORS
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Patent #:
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Issue Dt:
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08/23/1994
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Application #:
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07743532
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Filing Dt:
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08/08/1991
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Title:
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BASIC CELL FOR BICMOS GATE ARRAY
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Patent #:
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Issue Dt:
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05/19/1998
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Application #:
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08511172
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Filing Dt:
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08/04/1995
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Title:
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CAD AND SIMULATION SYSTEM FOR TARGETING IC DESIGNS TO MULTIPLE FABRICATION PROCESSES
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08797347
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Filing Dt:
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02/11/1997
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Title:
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SENSE AMPLIFYING METHODS AND SENSE AMPLIFICATION INTEGRATED DEVICES
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Patent #:
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Issue Dt:
|
02/10/1998
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Application #:
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08798816
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Filing Dt:
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02/11/1997
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Title:
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LOW POWER CONSUMING MEMORY SENSE AMPLIFYING CIRCUITRY
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Patent #:
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Issue Dt:
|
05/12/1998
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Application #:
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08806335
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Filing Dt:
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02/26/1997
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Title:
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HIGH SPEED MEMORY OUTPUT CIRCUITRY AND METHODS FOR IMPLEMENTING SAME
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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08829772
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Filing Dt:
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03/31/1997
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Publication #:
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Pub Dt:
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11/29/2001
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Title:
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METHOD AND APPARATUS FOR REDUCING PROCESS-INDUCED CHARGE BUILDUP
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08837611
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Filing Dt:
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04/21/1997
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Title:
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HIGH SPEED ADDRESSING BUFFER AND METHODS FOR IMPLEMENTING SAME
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08839151
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Filing Dt:
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04/23/1997
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Title:
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VOLTAGE SENSE AMPLIFIER AND METHODS FOR IMPLEMENTING THE SAME
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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08853276
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Filing Dt:
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05/09/1997
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Title:
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PROGRAMMABLE UNIVERSAL TEST INTERFACE AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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08885148
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Filing Dt:
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06/30/1997
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Title:
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CELL BASED ARRAY HAVING COMPUTE/DRIVE RATIOS OF N:1
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08928713
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Filing Dt:
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09/12/1997
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Title:
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SELF ADJUSTING PRE-CHARGE DELAY IN MEMORY CIRCUITS AND METHODS FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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03/16/1999
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Application #:
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08928714
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Filing Dt:
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09/12/1997
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Title:
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DISTRIBUTED BALANCED ADDRESS DETECTION AND CLOCK BUFFER CIRCUITRY AND METHODS FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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03/16/1999
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Application #:
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08937561
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Filing Dt:
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09/25/1997
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Title:
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LOW POWER CONSUMING MEMORY SENSE AMPLIFYING CIRCUITRY
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08956203
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Filing Dt:
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10/22/1997
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Title:
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INTEGRATED CIRCUIT LAYOUT METHODS AND LAYOUT STRUCTURES
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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08956981
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Filing Dt:
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10/24/1997
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Title:
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HIGH SPEED MEMORY SELF-TIMING CIRCUITRY AND METHODS FOR IMPLEMENTING THE SAME
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08984029
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Filing Dt:
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12/02/1997
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Title:
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POWER GROUND METALLIZATION ROUTING IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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09015427
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Filing Dt:
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01/29/1998
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Title:
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METHOD AND APPARATUS FOR ELIMINATING BITLINE VOLTAGE OFFSETS IN MEMORY DEVICES
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09099913
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Filing Dt:
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06/18/1998
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Title:
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PROGRAMMABLE UNIVERSAL TEST INTERFACE FOR TESTING MEMORIES WITH DIFFERENT TEST METHODOLOGIES
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09159264
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Filing Dt:
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09/23/1998
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Publication #:
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Pub Dt:
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11/29/2001
| | | | |
Title:
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CELL ARCHITECTURE WITH LOCAL INTERCONNECT AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09163890
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Filing Dt:
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09/30/1998
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Title:
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CELL BASED ARRAY COMPRISING LOGIC, TRANSFER AND DRIVE CELLS
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09164000
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Filing Dt:
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09/30/1998
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Title:
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CELL BASED ARRAY HAVING COMPUTE DRIVE RATIOS OF N:1
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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09177859
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Filing Dt:
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10/23/1998
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Title:
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LOW POWER DIFFERENTIAL SIGNAL TRANSITION TECHNIQUES FOR USE IN MEMORY DEVICES
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09207159
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Filing Dt:
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12/07/1998
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Title:
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REDUCTION OF PROCESS ANTENNA EFFECTS IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09273580
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Filing Dt:
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03/23/1999
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Title:
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CARRY CHAIN STANDARD CELL WITH CHARGE SHARING REDUCTION ARCHITECTURE
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09337999
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Filing Dt:
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06/22/1999
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Title:
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METHODS FOR DESIGNING STANDARD CELL TRANSISTOR STRUCTURES
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09368074
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Filing Dt:
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08/03/1999
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Title:
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POWER/GROUND METALLIZATION ROUTING IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09442877
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Filing Dt:
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11/18/1999
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Title:
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METHOD AND APPARATUS FOR ELIMINATING BITLINE VOLTAGE OFFSETS IN MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09594977
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Filing Dt:
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06/15/2000
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Title:
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Slew tolerant clock input buffer
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09615959
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Filing Dt:
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07/14/2000
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Title:
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Voltage tolerant input/output circuit
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09626264
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Filing Dt:
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07/25/2000
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Title:
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LOW-VOLTAGE DIFFERENTIAL I/O DEVICE
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09675574
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Filing Dt:
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09/29/2000
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Title:
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METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09678433
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Filing Dt:
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10/02/2000
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Title:
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INPUT/OUTPUT CELL GENERATOR
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09679059
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Filing Dt:
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10/02/2000
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Title:
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SEMICONDUCTOR CHIP INPUT/OUTPUT CELL DESIGN AND AUTOMATED GENERATION METHODS
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Patent #:
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Issue Dt:
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07/15/2003
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09703975
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10/31/2000
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Title:
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CELL ARCHITECTURE WITH LOCAL INTERCONNECT AND METHOD FOR MAKING SAME
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Patent #:
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10/28/2003
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Application #:
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09841797
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04/24/2001
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Title:
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SYSTEM AND METHOD FOR SETUP AND HOLD CHARACTERIZATION IN INTEGRATED CIRCUIT CELLS
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09896055
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Filing Dt:
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06/28/2001
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Publication #:
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Pub Dt:
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04/04/2002
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Title:
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METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09896444
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Filing Dt:
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06/28/2001
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Publication #:
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Pub Dt:
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04/04/2002
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Title:
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METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09929320
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08/13/2001
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Publication #:
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Pub Dt:
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12/27/2001
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Title:
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POWER/GROUND METALLIZATION ROUTING IN A SEMICONDUCTOR DEVICE
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Patent #:
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05/04/2004
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09991107
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11/16/2001
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Pub Dt:
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12/19/2002
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Title:
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LOW VOLTAGE DIFFERENTIAL SIGNALING CIRCUIT WITH MID-POINT BIAS
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07/05/2005
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10026245
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12/17/2001
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05/09/2002
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Title:
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MEMORIES HAVING REDUCED BITLINE VOLTAGE OFFSETS
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09/13/2005
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10026246
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12/17/2001
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Pub Dt:
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05/09/2002
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Title:
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METHODS FOR REDUCING BITLINE VOLTAGE OFFSETS IN MEMORY DEVICES
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12/06/2005
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10074517
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02/12/2002
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Title:
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SYSTEM AND METHOD FOR ASSURED BUILT IN SELF REPAIR OF MEMORIES
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09/09/2003
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10074559
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02/12/2002
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Title:
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ZERO POWER FUSE SENSING CIRCUIT FOR REDUNDANCY APPLICATIONS IN MEMORIES
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12/23/2003
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10077837
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02/15/2002
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01/08/2004
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Title:
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SYSTEM AND METHOD FOR IDENTIFICATION OF FAULTY OR WEAK MEMORY CELLS UNDER SIMULATED EXTREME OPERATING CONDITIONS
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Patent #:
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07/22/2003
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10113759
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03/27/2002
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Title:
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LOAD INDEPENDENT SINGLE ENDED SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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06/15/2004
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10170526
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Filing Dt:
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06/12/2002
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Title:
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METHOD AND APPARATUS FOR VOLTAGE CLAMPING IN FEEDBACK AMPLIFIERS USING RESISTORS
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09/09/2003
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10172206
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06/13/2002
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12/19/2002
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Title:
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METHOD AND APPARATUS FOR GAIN COMPENSATION AND CONTROL IN LOW VOLTAGE DIFFERENTIAL SIGNALING APPLICATIONS
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11/15/2005
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10179773
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06/24/2002
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Title:
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MEMORY COLUMN REDUNDANCY CIRCUITRY AND METHOD FOR IMPLEMENTING THE SAME
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10/28/2003
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10191931
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07/08/2002
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02/06/2003
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Title:
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METHOD AND APPARATUS FOR REDUCING PROCESS-INDUCED CHARGE BUILDUP
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01/06/2004
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Application #:
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10350497
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01/23/2003
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Title:
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METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM
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12/21/2004
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10364198
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02/10/2003
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08/12/2004
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Title:
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SYSTEM AND METHOD FOR ROW DECODE IN A MULTIPORT MEMORY
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03/08/2005
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10364719
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02/10/2003
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08/12/2004
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NEGATIVELY CHARGED WORDLINE FOR REDUCED SUBTHRESHOLD CURRENT
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09/07/2004
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10364720
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02/10/2003
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08/12/2004
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SYSTEM AND METHOD FOR LOW AREA SELF-TIMING IN MEMORY DEVICES
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09/06/2005
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10448636
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05/29/2003
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12/02/2004
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LEAKAGE CURRENT REDUCTION IN STANDARD CELLS
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08/23/2005
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10460626
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06/11/2003
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12/16/2004
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METHOD AND APPARATUS FOR REDUCING WRITE POWER CONSUMPTION IN RANDOM ACCESS MEMORIES
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08/02/2005
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10630949
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07/29/2003
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02/03/2005
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Title:
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VOLTAGE TOLERANT CIRCUIT FOR PROTECTING AN INPUT BUFFER
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03/01/2005
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10665862
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09/17/2003
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04/01/2004
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METHOD FOR IDENTIFICATION OF FAULTY OR WEAK FUNCTIONAL LOGIC ELEMENTS UNDER SIMULATED EXTREME OPERATING CONDITIONS
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10/18/2005
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10671029
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09/24/2003
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03/24/2005
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YIELD MAXIMIZATION IN THE MANUFACTURE OF INTEGRATED CIRCUITS
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02/21/2006
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10727760
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12/03/2003
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06/09/2005
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DUAL PORT MEMORY CORE CELL ARCHITECTURE WITH MATCHED BIT LINE CAPACITANCES
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02/28/2006
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10759339
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01/16/2004
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07/21/2005
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FEED-FORWARD CIRCUIT FOR REDUCING DELAY THROUGH AN INPUT BUFFER
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02/14/2006
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10833388
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04/27/2004
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10/27/2005
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Title:
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DYNAMICALLY ADAPTABLE MEMORY
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