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Patent Assignment Details
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Reel/Frame:049562/0154   Pages: 3
Recorded: 06/24/2019
Attorney Dkt #:TW0036
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 20
1
Patent #:
6950783
Issue Dt:
09/27/2005
Application #:
10708572
Filing Dt:
03/11/2004
Publication #:
US20050203858
Pub Dt:
09/15/2005
Title:
METHOD AND RELATED SYSTEM FOR SEMICONDUCTOR EQUIPMENT PREVENTION MAINTENANCE MANAGEMENT
2
Patent #:
6999897
Issue Dt:
02/14/2006
Application #:
10708573
Filing Dt:
03/11/2004
Publication #:
US20050203715
Pub Dt:
09/15/2005
Title:
METHOD AND RELATED SYSTEM FOR SEMICONDUCTOR EQUIPMENT EARLY WARNING MANAGEMENT
3
Patent #:
7049189
Issue Dt:
05/23/2006
Application #:
10708904
Filing Dt:
03/31/2004
Publication #:
US20050176203
Pub Dt:
08/11/2005
Title:
METHOD OF FABRICATING NON-VOLATILE MEMORY CELL ADAPTED FOR INTEGRATION OF DEVICES AND FOR MULTIPLE READ/WRITE OPERATIONS
4
Patent #:
7028433
Issue Dt:
04/18/2006
Application #:
10708944
Filing Dt:
04/02/2004
Publication #:
US20050126423
Pub Dt:
06/16/2005
Title:
ASEISMATIC DEVICE
5
Patent #:
6821849
Issue Dt:
11/23/2004
Application #:
10709309
Filing Dt:
04/28/2004
Publication #:
US20040197999
Pub Dt:
10/07/2004
Title:
[SPLIT GATE FLASH MEMORY CELL AND MANUFACUTIRNG METHOD THEREOF]
6
Patent #:
6838343
Issue Dt:
01/04/2005
Application #:
10709310
Filing Dt:
04/28/2004
Publication #:
US20040196720
Pub Dt:
10/07/2004
Title:
[FLASH MEMORY WITH SELF-ALIGNED SPLIT GATE AND METHODS FOR FABRICATING AND FOR OPERATING THE SAME]
7
Patent #:
7234196
Issue Dt:
06/26/2007
Application #:
10709335
Filing Dt:
04/29/2004
Publication #:
US20050168739
Pub Dt:
08/04/2005
Title:
TOOL FOR REMOVING PARTICLES FROM RETICLE
8
Patent #:
7038267
Issue Dt:
05/02/2006
Application #:
10709372
Filing Dt:
04/30/2004
Publication #:
US20050145921
Pub Dt:
07/07/2005
Title:
[NON-VOLATILE MEMORY CELL AND MANUFACTURING METHOD THEREOF]
9
Patent #:
6972260
Issue Dt:
12/06/2005
Application #:
10709469
Filing Dt:
05/07/2004
Publication #:
US20050250335
Pub Dt:
11/10/2005
Title:
[METHOD OF FABRICATING FLASH MEMORY CELL]
10
Patent #:
6914826
Issue Dt:
07/05/2005
Application #:
10709507
Filing Dt:
05/11/2004
Publication #:
US20040217412
Pub Dt:
11/04/2004
Title:
[FLASH MEMORY STRUCTURE AND OPERATING METHOD THEREOF]
11
Patent #:
7115214
Issue Dt:
10/03/2006
Application #:
10709552
Filing Dt:
05/13/2004
Publication #:
US20050103750
Pub Dt:
05/19/2005
Title:
METHOD OF FORMING BARRIER LAYER
12
Patent #:
6913974
Issue Dt:
07/05/2005
Application #:
10709590
Filing Dt:
05/17/2004
Publication #:
US20040197994
Pub Dt:
10/07/2004
Title:
[FLASH MEMORY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF]
13
Patent #:
7344579
Issue Dt:
03/18/2008
Application #:
10709607
Filing Dt:
05/18/2004
Publication #:
US20050144915
Pub Dt:
07/07/2005
Title:
[PIPE TRAP]
14
Patent #:
6893918
Issue Dt:
05/17/2005
Application #:
10709639
Filing Dt:
05/19/2004
Title:
[METHOD OF FABRICATING A FLASH MEMORY]
15
Patent #:
6984559
Issue Dt:
01/10/2006
Application #:
10709640
Filing Dt:
05/19/2004
Publication #:
US20050176200
Pub Dt:
08/11/2005
Title:
[METHOD OF FABRICATING A FLASH MEMORY]
16
Patent #:
6995086
Issue Dt:
02/07/2006
Application #:
10710237
Filing Dt:
06/28/2004
Publication #:
US20050148168
Pub Dt:
07/07/2005
Title:
METHOD FOR FABRICATING A THROUGH HOLE ON A SEMICONDUCTOR SUBSTRATE
17
Patent #:
7145644
Issue Dt:
12/05/2006
Application #:
10710243
Filing Dt:
06/29/2004
Publication #:
US20050190348
Pub Dt:
09/01/2005
Title:
DEVICE AND METHOD FOR TESTING AN EXPOSURE APPARATUS
18
Patent #:
7182873
Issue Dt:
02/27/2007
Application #:
10710402
Filing Dt:
07/08/2004
Publication #:
US20060006115
Pub Dt:
01/12/2006
Title:
METHOD OF FLUORIDE-CONTAINING WASTEWATER TREATMENT
19
Patent #:
6913516
Issue Dt:
07/05/2005
Application #:
10710508
Filing Dt:
07/16/2004
Title:
[DUMMY PROCESS AND POLISHING-PAD CONDITIONING PROCESS FOR CHEMICAL MECHANICAL POLISHING APPARATUS]
20
Patent #:
6963213
Issue Dt:
11/08/2005
Application #:
10710670
Filing Dt:
07/28/2004
Publication #:
US20050231190
Pub Dt:
10/20/2005
Title:
[AUTO-RECOVERY WAFER TESTING APPARATUS AND WAFER TESTING METHOD]
Assignor
1
POWERCHIP SEMICONDUCTOR CORP.
Exec Dt:
08/09/2010
Assignee
1
POWERCHIP TECHNOLOGY CORPORATION
NO. 12, LI-HSIN ROAD I, HSINCHU SCIENCE PARK,
HSINCHU, TAIWAN
Correspondence name and address
JCIPRNET
P.O. BOX 600 TAIPEI GUTING
TAIPEI CITY, 10099 TAIWAN

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