|
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|
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10413800
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
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Title:
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METHOD OF PROGRAMMING DUAL CELL MEMORY DEVICE TO STORE MULTIPLE DATA STATES PER CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
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Application #:
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10413818
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
|
09/18/2003
| | | | |
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Title:
|
MEMORY DEVICE WITH ACTIVE AND PASSIVE LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
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Application #:
|
10413829
|
Filing Dt:
|
04/15/2003
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Publication #:
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Pub Dt:
|
09/25/2003
| | | | |
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Title:
|
MEMORY DEVICE
|
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|
|
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Patent #:
|
|
Issue Dt:
|
01/04/2005
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Application #:
|
10413841
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Filing Dt:
|
04/15/2003
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Publication #:
|
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Pub Dt:
|
02/12/2004
| | | | |
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Title:
|
MEMORY DEVICE WITH ACTIVE PASSIVE LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
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Application #:
|
10414353
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Filing Dt:
|
04/15/2003
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Publication #:
|
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Pub Dt:
|
09/25/2003
| | | | |
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Title:
|
MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
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Application #:
|
10422090
|
Filing Dt:
|
04/24/2003
|
|
Title:
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METHOD OF CONTROLLING PROGRAM THRESHOLD VOLTAGE DISTRIBUTION OF A DUAL CELL MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10422092
|
Filing Dt:
|
04/24/2003
|
|
Title:
|
METHOD OF DUAL CELL MEMORY DEVICE OPERATION FOR IMPROVED END-OF-LIFE READ MARGIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10422276
|
Filing Dt:
|
04/24/2003
|
|
Title:
|
METHOD OF PROGRAMMING AND READING A DUAL CELL MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10422489
|
Filing Dt:
|
04/24/2003
|
|
Title:
|
METHOD OF PROGRAMMING A DUAL CELL MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10429140
|
Filing Dt:
|
05/03/2003
|
|
Title:
|
STRUCTURE AND METHOD FOR A TWO-BIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10429150
|
Filing Dt:
|
05/03/2003
|
|
Title:
|
METHOD FOR REDUCING SHORT CHANNEL EFFECTS IN MEMORY CELLS AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
10429447
|
Filing Dt:
|
05/05/2003
|
|
Title:
|
PROCESS FOR REDUCING HYDROGEN CONTAMINATION IN DIELECTRIC MATERIALS IN MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10430471
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
METHOD OF FORMATION OF GATE STACK SPACER AND CHARGE STORAGE MATERIALS HAVING REDUCED HYDROGEN CONTENT IN CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10430582
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
TRENCH SIDE WALL CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10430604
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
MEMORY DEVICE WITH REDUCED OPERATING VOLTAGE HAVING DIELECTRIC STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10431065
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
METHOD TO OBTAIN TEMPERATURE INDEPENDENT PROGRAM THRESHOLD VOLTAGE DISTRIBUTION USING TEMPERATURE DEPENDENT VOLTAGE REFERENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
10431320
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
NON-VOLATILE MEMORY READ CIRCUIT WITH END OF LIFE SIMULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
10431321
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
A METHOD FOR MANUFACTURING A DOUBLE BITLINE IMPLANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10431322
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING SHORT CHANNEL EFFECT ON A FLOATING GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10436786
|
Filing Dt:
|
05/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
|
Title:
|
ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHOD OF FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10437896
|
Filing Dt:
|
05/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10438942
|
Filing Dt:
|
05/16/2003
|
|
Title:
|
LASER THERMAL ANNEALING METHODS FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10452877
|
Filing Dt:
|
06/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
PLANAR POLYMER MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10454517
|
Filing Dt:
|
06/05/2003
|
|
Title:
|
SEMICONDUTOR DEVICE HAVING CONDUCTIVE STRUCTURES FORMED NEAR A GATE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10455310
|
Filing Dt:
|
06/06/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10459102
|
Filing Dt:
|
06/11/2003
|
|
Title:
|
MEMORY DEVICE HAVING A THIN TOP DIELECTRIC AND METHOD OF ERASING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10459576
|
Filing Dt:
|
06/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10460278
|
Filing Dt:
|
06/12/2003
|
|
Title:
|
STRUCTURE AND METHOD FOR PREVENTING UV RADIATION DAMAGE IN A MEMORY CELL AND IMPROVING CONTACT CD CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10460279
|
Filing Dt:
|
06/12/2003
|
|
Title:
|
STRUCTURE AND METHOD FOR PREVENTING UV RADIATION DAMAGE AND INCREASING DATA RETENTION IN MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
10460282
|
Filing Dt:
|
06/12/2003
|
|
Title:
|
STRUCTURE AND METHOD FOR PREVENTING PROCESS-INDUCED UV RADIATION DAMAGE IN A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10463643
|
Filing Dt:
|
06/17/2003
|
|
Title:
|
METHOD OF FABRICATING A PLANAR STRUCTURE CHARGE TRAPPING MEMORY CELL ARRAY WITH RECTANGULAR GATES AND REDUCED BIT LINE RESISTANCE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10475997
|
Filing Dt:
|
04/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
|
Title:
|
Remote maintenance system and remote maintenance method for semiconductor manufacturing apparatus
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10544902
|
Filing Dt:
|
05/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
|
Title:
|
Radiation-sensitive resin composition, process for producing the same and process for producing semiconductor device therewith
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
10600065
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
MEMORY WITH A CORE-BASED VIRTUAL GROUND AND DYNAMIC REFERENCE SENSING SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10603136
|
Filing Dt:
|
06/23/2003
|
|
Title:
|
SIMULTANEOUS EXECUTION COMMAND MODES IN A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10614177
|
Filing Dt:
|
07/08/2003
|
|
Title:
|
FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10614397
|
Filing Dt:
|
07/07/2003
|
|
Title:
|
POLYMER MEMORY DEVICE FORMED IN VIA OPENING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10614484
|
Filing Dt:
|
07/07/2003
|
|
Title:
|
SILICON CONTAINING MATERIAL FOR PATTERNING POLYMERIC MEMORY ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10616804
|
Filing Dt:
|
07/09/2003
|
|
Title:
|
METHOD FOR FABRICATING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10617450
|
Filing Dt:
|
07/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
UNDOPED OXIDE LINER/BPSG FOR IMPROVED DATA RETENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10617451
|
Filing Dt:
|
07/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
PECVD SILICON-RICH OXIDE LAYER FOR REDUCED UV CHARGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10617971
|
Filing Dt:
|
07/10/2003
|
|
Title:
|
PROGRAMMING OF A FLASH MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10618156
|
Filing Dt:
|
07/11/2003
|
|
Title:
|
MEMORY STRUCTURE HAVING TUNABLE INTERLAYER DIELECTRIC AND METHOD FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10618191
|
Filing Dt:
|
07/10/2003
|
|
Title:
|
FLASH MEMORY CELL HAVING REDUCED LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10618514
|
Filing Dt:
|
07/11/2003
|
|
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING TRIPLE LDD STRUCTURE AND LOWER GATE RESISTANCE FORMED WITH A SINGLE IMPLANT PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10619797
|
Filing Dt:
|
07/14/2003
|
|
Title:
|
PARTIALLY DE-COUPLED CORE AND PERIPHERY GATE MODULE PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10631199
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10631812
|
Filing Dt:
|
08/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
NONVOLATILE MEMORY HAVING A TRAP LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10631856
|
Filing Dt:
|
08/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE SUPPLYING PROPER PROGRAM POTENTIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10633535
|
Filing Dt:
|
08/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF BLOCKS AND A SENSING CIRCUIT PROVIDED IN EACH OF THE BLOCKS FOR
COMPARING DATA WITH A REFERENCE SIGNAL HAVING A LOAD IMPOSED
THEREON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10634042
|
Filing Dt:
|
08/04/2003
|
|
Title:
|
A METHOD OF FABRICATING A DUAL-LEVEL STACKED FLASH MEMORY CELL WITH A MOSFET STORAGE TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10635089
|
Filing Dt:
|
08/06/2003
|
|
Title:
|
MEMORY DEVICE AND METHOD OF SIMULTANEOUS FABRICATION OF CORE AND PERIPHERY OF SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10635431
|
Filing Dt:
|
08/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
CONTROL METHOD OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10635781
|
Filing Dt:
|
08/06/2003
|
|
Title:
|
MEMORY DEVICE HAVING SILICIDED BITLINES AND METHOD OF FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10636162
|
Filing Dt:
|
08/07/2003
|
|
Title:
|
TEST STRUCTURE FOR DETERMINING ELECTROMIGRATION AND INTERLAYER DIELECTRIC FAILURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10636336
|
Filing Dt:
|
08/06/2003
|
|
Title:
|
STRUCTURE AND METHOD TO REDUCE DRAIN INDUCED BARRIER LOWERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10636337
|
Filing Dt:
|
08/06/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
LOW POWER CHARGE PUMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10643967
|
Filing Dt:
|
08/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10646080
|
Filing Dt:
|
08/22/2003
|
|
Title:
|
USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10649994
|
Filing Dt:
|
08/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY CAPABLE OF BEING DRIVEN AT LOW VOLTAGE AND ITS MANUFACTURE METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10650049
|
Filing Dt:
|
08/26/2003
|
|
Title:
|
CAM (CONTENT ADDRESSABLE MEMORY) CELLS AS PART OF CORE ARRAY IN FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10650072
|
Filing Dt:
|
08/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A MEMORY INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10652035
|
Filing Dt:
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09/02/2003
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Publication #:
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Pub Dt:
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06/10/2004
| | | | |
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Title:
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MEMORY CIRCUIT WITH REDUNDANT CONFIGURATION
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10654739
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Filing Dt:
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09/03/2003
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Title:
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PATTERNING FOR ELONGATED VSS CONTACT ON FLASH MEMORY
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10655179
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Filing Dt:
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09/04/2003
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Title:
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MEMORY CELL STRUCTURE HAVING NITRIDE LAYER WITH REDUCED CHARGE LOSS AND METHOD FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10655936
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Filing Dt:
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09/04/2003
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Title:
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METHOD OF FABRICATING A FLOATING GATE
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Patent #:
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Issue Dt:
|
02/08/2005
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Application #:
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10658428
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
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05/27/2004
| | | | |
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Title:
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SEMICONDUCTOR MEMORY ENABLING CORRECT SUBSTITUTION OF REDUNDANT CELL ARRAY
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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10658506
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Filing Dt:
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09/09/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
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Title:
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MEMORY DEVICE HAVING HIGH WORK FUNCTION GATE AND METHOD OF ERASING SAME
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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10658882
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Filing Dt:
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09/09/2003
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Title:
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METHOD AND APPARATUS FOR COUPLING TO A COMMON LINE IN AN ARRAY
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Patent #:
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Issue Dt:
|
08/19/2008
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Application #:
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10658936
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Filing Dt:
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09/09/2003
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Title:
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FLASH MEMORY WITH HIGH-K DIELECTRIC MATERIAL BETWEEN SUBSTRATE AND GATE
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Patent #:
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Issue Dt:
|
05/15/2007
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Application #:
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10658937
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Filing Dt:
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09/09/2003
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Title:
|
METHOD AND APPARATUS FOR COUPLING TO A SOURCE LINE IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
|
11/02/2004
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Application #:
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10660420
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Filing Dt:
|
09/10/2003
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Title:
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HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
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Patent #:
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Issue Dt:
|
09/13/2005
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Application #:
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10661720
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Filing Dt:
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09/11/2003
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Title:
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A FLASH MEMORY CELL WITH DRAIN AND SOURCE FORMED BY DIFFUSION OF A DOPANT FROM A SILICIDE
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|
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Patent #:
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Issue Dt:
|
04/11/2006
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Application #:
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10662011
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Filing Dt:
|
09/11/2003
|
|
Title:
|
METHOD FOR FABRICATING A MEMORY DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
03/29/2005
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Application #:
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10662810
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Filing Dt:
|
09/16/2003
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Publication #:
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Pub Dt:
|
05/13/2004
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
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Patent #:
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|
Issue Dt:
|
04/26/2005
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Application #:
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10672093
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Filing Dt:
|
09/26/2003
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
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|
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Patent #:
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|
Issue Dt:
|
08/30/2005
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Application #:
|
10676612
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Filing Dt:
|
10/01/2003
|
|
Title:
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ORGANIC MEMORY CELL FORMATION ON AG SUBSTRATE
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|
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Patent #:
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|
Issue Dt:
|
12/27/2005
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Application #:
|
10677031
|
Filing Dt:
|
10/01/2003
|
|
Title:
|
MEMORY DEVICE AND METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10677042
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Filing Dt:
|
10/01/2003
|
|
Title:
|
SELF ASSEMBLY OF CONDUCTING POLYMER FOR FORMATION OF POLYMER MEMORY CELL
|
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|
|
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Patent #:
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|
Issue Dt:
|
12/06/2005
|
Application #:
|
10677073
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Filing Dt:
|
10/01/2003
|
|
Title:
|
MEMORY DEVICE AND METHOD
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/22/2005
|
Application #:
|
10677790
|
Filing Dt:
|
10/02/2003
|
|
Publication #:
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Pub Dt:
|
04/07/2005
| | | | |
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Title:
|
MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVERERASED CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10678446
|
Filing Dt:
|
10/03/2003
|
|
Title:
|
EFFICIENT AND ACCURATE SENSING CIRCUIT AND TECHNIQUE FOR LOW VOLTAGE FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10679179
|
Filing Dt:
|
10/03/2003
|
|
Title:
|
CIRCUIT AND TECHNIQUE FOR ACCURATELY SENSING LOW VOLTAGE FLASH MEMORY DEVICES
|
|
|
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|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10679774
|
Filing Dt:
|
10/06/2003
|
|
Title:
|
FLASH MEMORY DEVICE AND METHOD OF FABRICATION THEREOF INCLUDING A BOTTOM OXIDE LAYER WITH TWO REGIONS WITH DIFFERENT CONCENTRATIONS OF NITROGEN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10682299
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10683631
|
Filing Dt:
|
10/10/2003
|
|
Title:
|
RECESSED CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10683649
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
RECESS CHANNEL FLASH ARCHITECTURE FOR REDUCED SHORT CHANNEL EFFECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10684890
|
Filing Dt:
|
10/14/2003
|
|
Title:
|
NON VOLATILE CHARGE TRAPPING DIELECTRIC MEMORY CELL STRUCTURE WITH GATE HOLE INJECTION ERASE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10685044
|
Filing Dt:
|
10/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10696234
|
Filing Dt:
|
10/28/2003
|
|
Title:
|
METHOD FOR FORMING A DIELECTRIC SPACER IN A NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10699903
|
Filing Dt:
|
11/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SIDEWALL FORMATION FOR HIGH DENSITY POLYMER MEMORY ELEMENT ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10700021
|
Filing Dt:
|
11/03/2003
|
|
Title:
|
MEMORY ELEMENT FORMATION WITH PHOTOSENSITIVE POLYMER DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10701780
|
Filing Dt:
|
11/05/2003
|
|
Title:
|
METHOD AND STRUCTURE FOR PROTECTING NROM DEVICES FROM INDUCED CHARGE DAMAGE DURING DEVICE FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10703860
|
Filing Dt:
|
11/07/2003
|
|
Title:
|
METHOD AND SYSTEM FOR TESTING ARTICLES OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
10705881
|
Filing Dt:
|
11/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10714909
|
Filing Dt:
|
11/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10716209
|
Filing Dt:
|
11/18/2003
|
|
Title:
|
TIGHTLY SPACED GATE FORMATION THROUGH DAMASCENE PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10716230
|
Filing Dt:
|
11/18/2003
|
|
Title:
|
DUAL CELL MEMORY DEVICE HAVING A TOP DIELECTRIC STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10717622
|
Filing Dt:
|
11/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STORING TWO-BIT INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10718707
|
Filing Dt:
|
11/24/2003
|
|
Title:
|
METHODS FOR FORMING NITROGEN-RICH REGIONS IN NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
|
|
