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Reel/Frame:035201/0159   Pages: 226
Recorded: 03/13/2015
Attorney Dkt #:3483.276
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 1788
Page 4 of 18
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1
Patent #:
6284602
Issue Dt:
09/04/2001
Application #:
09399526
Filing Dt:
09/20/1999
Title:
PROCESS TO REDUCE POST CYCLING PROGRAM VT DISPERSION FOR NAND FLASH MEMORY DEVICES
2
Patent #:
6172914
Issue Dt:
01/09/2001
Application #:
09404078
Filing Dt:
09/23/1999
Title:
CONCURRENT ERASE VERIFY SCHEME FOR FLASH MEMORY APPLICATIONS
3
Patent #:
6049479
Issue Dt:
04/11/2000
Application #:
09404080
Filing Dt:
09/23/1999
Title:
OPERATIONAL APPROACH FOR THE SUPPRESSION OF BI-DIRECTIONAL TUNNEL OXIDE STRESS OF A FLASH CELL
4
Patent #:
6369416
Issue Dt:
04/09/2002
Application #:
09404394
Filing Dt:
09/23/1999
Title:
SEMICONDUCTOR DEVICE WITH CONTACTS HAVING A SLOPED PROFILE
5
Patent #:
6342415
Issue Dt:
01/29/2002
Application #:
09404395
Filing Dt:
09/23/1999
Publication #:
US20020025618
Pub Dt:
02/28/2002
Title:
METHOD AND SYSTEM FOR PROVIDING REDUCED-SIZED CONTACTS IN A SEMICONDUCTOR DEVICE
6
Patent #:
6266275
Issue Dt:
07/24/2001
Application #:
09410512
Filing Dt:
09/30/1999
Title:
DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
7
Patent #:
6452441
Issue Dt:
09/17/2002
Application #:
09411169
Filing Dt:
10/01/1999
Title:
LOW THRESHOLD VOLTAGE DEVICE WITH CHARGE PUMP FOR REDUCING STANDBY CURRENT IN AN INTEGRATED CIRCUIT HAVING REDUCED SUPPLY VOLTAGE
8
Patent #:
6177316
Issue Dt:
01/23/2001
Application #:
09412278
Filing Dt:
10/05/1999
Title:
POST BARRIER METAL CONTACT IMPLANTATION TO MINIMIZE OUT DIFFUSION FOR NAND DEVICE
9
Patent #:
6235584
Issue Dt:
05/22/2001
Application #:
09412544
Filing Dt:
10/05/1999
Title:
METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DEVICE
10
Patent #:
6122198
Issue Dt:
09/19/2000
Application #:
09413182
Filing Dt:
10/05/1999
Title:
BIT BY BIT APDE VERIFY FOR FLASH MEMORY APPLICATIONS
11
Patent #:
6506683
Issue Dt:
01/14/2003
Application #:
09413621
Filing Dt:
10/06/1999
Title:
IN-SITU PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INTEGRAL REMOVAL OF ANTIREFLECTION AND ETCH STOP LAYERS
12
Patent #:
6291296
Issue Dt:
09/18/2001
Application #:
09416382
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS BEFORE CONTACT CMP
13
Patent #:
6136649
Issue Dt:
10/24/2000
Application #:
09416389
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS AFTER CONTACT CMP
14
Patent #:
6275415
Issue Dt:
08/14/2001
Application #:
09416563
Filing Dt:
10/12/1999
Title:
MULTIPLE BYTE CHANNEL HOT ELECTRON PROGRAMMING USING RAMPED GATE AND SOURCE BIAS VOLTAGE
15
Patent #:
6197635
Issue Dt:
03/06/2001
Application #:
09417130
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED MASKING AND WITHOUT ARC LOSS IN PERIPHERAL CIRCUITRY REGION
16
Patent #:
6235587
Issue Dt:
05/22/2001
Application #:
09417131
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED ARC LOSS IN PERIPHERAL CIRCUITRY REGION
17
Patent #:
6200857
Issue Dt:
03/13/2001
Application #:
09417132
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITHOUT ARC LOSS IN PERIPHERAL CIRCUIT REGION
18
Patent #:
6046932
Issue Dt:
04/04/2000
Application #:
09417273
Filing Dt:
10/13/1999
Title:
CIRCUIT IMPLEMENTATION TO QUENCH BIT LINE LEAKAGE CURRENT IN PROGRAMMING AND OVER-ERASE CORRECTION MODES IN FLASH EEPROM
19
Patent #:
6118694
Issue Dt:
09/12/2000
Application #:
09417731
Filing Dt:
10/14/1999
Title:
DISTRIBUTING CFI DEVICES IN EXISTING DECODERS
20
Patent #:
6144606
Issue Dt:
11/07/2000
Application #:
09417732
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR BI-DIRECTIONAL VOLTAGE REGULATION DETECTION
21
Patent #:
6147906
Issue Dt:
11/14/2000
Application #:
09419695
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR SAVING OVERHEAD PROGRAM TIME IN A MEMORY DEVICE
22
Patent #:
6185130
Issue Dt:
02/06/2001
Application #:
09420209
Filing Dt:
10/18/1999
Title:
PROGRAMMABLE CURRENT SOURCE
23
Patent #:
6255165
Issue Dt:
07/03/2001
Application #:
09420220
Filing Dt:
10/18/1999
Title:
NITRIDE PLUG TO REDUCE GATE EDGE LIFTING
24
Patent #:
6662262
Issue Dt:
12/09/2003
Application #:
09420535
Filing Dt:
10/19/1999
Title:
OTP SECTOR DOUBLE PROTECTION FOR A SIMULTANEOUS OPERATION FLASH MEMORY
25
Patent #:
6475915
Issue Dt:
11/05/2002
Application #:
09420687
Filing Dt:
10/19/1999
Title:
ONO ETCH USING CL2/HE CHEMISTRY
26
Patent #:
6125055
Issue Dt:
09/26/2000
Application #:
09421105
Filing Dt:
10/19/1999
Title:
SECTOR WRITE PROTECT CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
27
Patent #:
6201753
Issue Dt:
03/13/2001
Application #:
09421142
Filing Dt:
10/19/1999
Title:
LATCHING CAM DATA IN A FLASH MEMORY DEVICE
28
Patent #:
6118702
Issue Dt:
09/12/2000
Application #:
09421151
Filing Dt:
10/19/1999
Title:
SOURCE BIAS COMPENSATION FOR PAGE MODE READ OPERATION IN A FLASH MEMORY DEVICE
29
Patent #:
6550028
Issue Dt:
04/15/2003
Application #:
09421470
Filing Dt:
10/19/1999
Title:
ARRAY VT MODE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
30
Patent #:
6285585
Issue Dt:
09/04/2001
Application #:
09421471
Filing Dt:
10/19/1999
Title:
OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
31
Patent #:
6331950
Issue Dt:
12/18/2001
Application #:
09421757
Filing Dt:
10/19/1999
Title:
WRITE PROTECT INPUT IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
32
Patent #:
6571307
Issue Dt:
05/27/2003
Application #:
09421758
Filing Dt:
10/19/1999
Title:
MULTIPLE PURPOSE BUS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
33
Patent #:
6163478
Issue Dt:
12/19/2000
Application #:
09421774
Filing Dt:
10/19/1999
Title:
COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
34
Patent #:
6327181
Issue Dt:
12/04/2001
Application #:
09421775
Filing Dt:
10/19/1999
Title:
REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
35
Patent #:
6111787
Issue Dt:
08/29/2000
Application #:
09421776
Filing Dt:
10/19/1999
Title:
ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
36
Patent #:
6185128
Issue Dt:
02/06/2001
Application #:
09421984
Filing Dt:
10/19/1999
Title:
REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
37
Patent #:
6359808
Issue Dt:
03/19/2002
Application #:
09421985
Filing Dt:
10/19/1999
Title:
LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
38
Patent #:
6259633
Issue Dt:
07/10/2001
Application #:
09422198
Filing Dt:
10/19/1999
Title:
SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
39
Patent #:
6118698
Issue Dt:
09/12/2000
Application #:
09422199
Filing Dt:
10/19/1999
Title:
OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
40
Patent #:
6248635
Issue Dt:
06/19/2001
Application #:
09426205
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
41
Patent #:
6218227
Issue Dt:
04/17/2001
Application #:
09426239
Filing Dt:
10/25/1999
Title:
METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
42
Patent #:
6180538
Issue Dt:
01/30/2001
Application #:
09426240
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE USING RAPID-THERMAL-CHEMICAL-VAPOR-DEPOSITION
43
Patent #:
6207502
Issue Dt:
03/27/2001
Application #:
09426255
Filing Dt:
10/25/1999
Title:
METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE
44
Patent #:
6326268
Issue Dt:
12/04/2001
Application #:
09426427
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING A MONOS FLASH CELL USING SHALLOW TRENCH ISOLATION
45
Patent #:
6248628
Issue Dt:
06/19/2001
Application #:
09426430
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
46
Patent #:
6265268
Issue Dt:
07/24/2001
Application #:
09426672
Filing Dt:
10/25/1999
Title:
HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
47
Patent #:
6297143
Issue Dt:
10/02/2001
Application #:
09426743
Filing Dt:
10/25/1999
Title:
PROCESS FOR FORMING A BIT-LINE IN A MONOS DEVICE
48
Patent #:
6117730
Issue Dt:
09/12/2000
Application #:
09427402
Filing Dt:
10/25/1999
Title:
INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
49
Patent #:
6242305
Issue Dt:
06/05/2001
Application #:
09427404
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
50
Patent #:
6448609
Issue Dt:
09/10/2002
Application #:
09429244
Filing Dt:
10/28/1999
Title:
METHOD AND SYSTEM FOR PROVIDINNG A POLYSILICON STRINGER MONITOR
51
Patent #:
6399446
Issue Dt:
06/04/2002
Application #:
09429722
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A METALLIC HARD MASK
52
Patent #:
6147907
Issue Dt:
11/14/2000
Application #:
09430336
Filing Dt:
10/29/1999
Title:
BIASING SCHEME TO REDUCE STRESS ON NON-SELECTED CELLS DURING READ
53
Patent #:
6867097
Issue Dt:
03/15/2005
Application #:
09430366
Filing Dt:
10/28/1999
Title:
METHOD OF MAKING A MEMORY CELL WITH POLISHED INSULATOR LAYER
54
Patent #:
6329273
Issue Dt:
12/11/2001
Application #:
09430410
Filing Dt:
10/29/1999
Title:
SOLID-SOURCE DOPING FOR SOURCE/DRAIN TO ELIMINATE IMPLANT DAMAGE
55
Patent #:
6436766
Issue Dt:
08/20/2002
Application #:
09430493
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A POLYSILICON HARD MASK
56
Patent #:
6180454
Issue Dt:
01/30/2001
Application #:
09430765
Filing Dt:
10/29/1999
Title:
METHOD FOR FORMING FLASH MEMORY DEVICES
57
Patent #:
6551923
Issue Dt:
04/22/2003
Application #:
09430845
Filing Dt:
11/01/1999
Title:
DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
58
Patent #:
6441418
Issue Dt:
08/27/2002
Application #:
09430848
Filing Dt:
11/01/1999
Title:
SPACER NARROWED, DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
59
Patent #:
6628417
Issue Dt:
09/30/2003
Application #:
09431269
Filing Dt:
11/01/1999
Title:
DATA COMMUNICATION APPARATUS, IMAGE SERVER, CONTROL METHOD, STORAGE MEDIUM, AND IMAGE SYSTEM
60
Patent #:
6319775
Issue Dt:
11/20/2001
Application #:
09433037
Filing Dt:
10/25/1999
Title:
NITRIDATION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE
61
Patent #:
6406960
Issue Dt:
06/18/2002
Application #:
09433041
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE HAVING A SILICON-RICH SILICON NITRIDE LAYER
62
Patent #:
6458677
Issue Dt:
10/01/2002
Application #:
09433186
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE
63
Patent #:
6232632
Issue Dt:
05/15/2001
Application #:
09436503
Filing Dt:
11/09/1999
Title:
DOUBLE DENSITY NON-VOLATILE MEMORY CELLS
64
Patent #:
6309949
Issue Dt:
10/30/2001
Application #:
09440934
Filing Dt:
11/16/1999
Title:
SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
65
Patent #:
6236596
Issue Dt:
05/22/2001
Application #:
09461376
Filing Dt:
12/15/1999
Title:
BIASING METHOD AND STRUCTURE FOR REDUCING BAND-TO-BAND AND/OR AVALANCHE CURRENTS DURING THE ERASE OF FLASH MEMORY DEVICES
66
Patent #:
6225161
Issue Dt:
05/01/2001
Application #:
09470568
Filing Dt:
12/22/1999
Title:
FULLY RECESSED SEMICONDUCTOR METHOD FOR LOW POWER APPLICATIONS WITH SINGLE WRAP AROUND BURIED DRAIN REGION
67
Patent #:
6274433
Issue Dt:
08/14/2001
Application #:
09476121
Filing Dt:
01/03/2000
Title:
METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
68
Patent #:
6238978
Issue Dt:
05/29/2001
Application #:
09476584
Filing Dt:
01/03/2000
Title:
USE OF ETCH TO BLUNT GATE CORNERS
69
Patent #:
6518072
Issue Dt:
02/11/2003
Application #:
09476906
Filing Dt:
01/03/2000
Title:
DEPOSITED SCREEN OXIDE FOR REDUCING GATE EDGE LIFTING
70
Patent #:
6410956
Issue Dt:
06/25/2002
Application #:
09478864
Filing Dt:
01/07/2000
Title:
METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
71
Patent #:
6638358
Issue Dt:
10/28/2003
Application #:
09483176
Filing Dt:
01/13/2000
Title:
METHOD AND SYSTEM FOR PROCESSING A SEMICONDUCTOR DEVICE
72
Patent #:
6225646
Issue Dt:
05/01/2001
Application #:
09483557
Filing Dt:
01/14/2000
Title:
Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base
73
Patent #:
6376308
Issue Dt:
04/23/2002
Application #:
09487073
Filing Dt:
01/19/2000
Title:
Process for fabricating an eeprom device having a pocket substrate region
74
Patent #:
6168993
Issue Dt:
01/02/2001
Application #:
09487922
Filing Dt:
01/19/2000
Title:
Process for fabricating a semiconductor device having a graded junction
75
Patent #:
6465835
Issue Dt:
10/15/2002
Application #:
09487964
Filing Dt:
01/18/2000
Title:
CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
76
Patent #:
6236603
Issue Dt:
05/22/2001
Application #:
09489232
Filing Dt:
01/21/2000
Title:
High speed charging of core cell drain lines in a memory device
77
Patent #:
6212108
Issue Dt:
04/03/2001
Application #:
09490340
Filing Dt:
01/24/2000
Title:
Distributed voltage charge circuits to reduce sensing time in a memory device
78
Patent #:
6160740
Issue Dt:
12/12/2000
Application #:
09490351
Filing Dt:
01/24/2000
Title:
METHOD TO PROVIDE A REDUCED CONSTANT E-FIELD DURING ERASE OF EEPROMS FOR RELIABILITY IMPROVEMENT
79
Patent #:
6178117
Issue Dt:
01/23/2001
Application #:
09490352
Filing Dt:
01/24/2000
Title:
Background correction for charge gain and loss
80
Patent #:
6137727
Issue Dt:
10/24/2000
Application #:
09490353
Filing Dt:
01/24/2000
Title:
Reduction of oxide stress through the use of forward biased body voltage
81
Patent #:
6509604
Issue Dt:
01/21/2003
Application #:
09491457
Filing Dt:
01/26/2000
Title:
NOVEL NITRIDATION BARRIERS FOR NITRIDATED TUNNEL OXIDE FOR CIRCUITRY FOR FLASH TECHNOLOGY AND FOR LOCOS/STI ISOLATION
82
Patent #:
6812521
Issue Dt:
11/02/2004
Application #:
09492243
Filing Dt:
01/27/2000
Title:
METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF FLASH MEMORY CELL DEVICES
83
Patent #:
6329687
Issue Dt:
12/11/2001
Application #:
09492353
Filing Dt:
01/27/2000
Title:
Two bit flash cell with two floating gate regions
84
Patent #:
6787840
Issue Dt:
09/07/2004
Application #:
09492931
Filing Dt:
01/27/2000
Title:
NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY TECHOLOGY CIRCUITRY
85
Patent #:
6359307
Issue Dt:
03/19/2002
Application #:
09493436
Filing Dt:
01/29/2000
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS AND INTERCONNECTION LINES USING DUAL DAMASCENE TECHNIQUES
86
Patent #:
6294430
Issue Dt:
09/25/2001
Application #:
09495213
Filing Dt:
01/31/2000
Title:
Nitridization of the pre-ddi screen oxide
87
Patent #:
6240016
Issue Dt:
05/29/2001
Application #:
09495214
Filing Dt:
01/31/2000
Title:
Method to reduce read gate disturb for flash eeprom application
88
Patent #:
6198664
Issue Dt:
03/06/2001
Application #:
09495215
Filing Dt:
01/31/2000
Title:
APDE scheme for flash memory application
89
Patent #:
6285588
Issue Dt:
09/04/2001
Application #:
09495216
Filing Dt:
01/31/2000
Title:
Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
90
Patent #:
6160750
Issue Dt:
12/12/2000
Application #:
09498205
Filing Dt:
02/04/2000
Title:
Noise reduction during simultaneous operation of a flash memory device
91
Patent #:
6243316
Issue Dt:
06/05/2001
Application #:
09501159
Filing Dt:
02/09/2000
Title:
Voltage boost reset circuit for a flash memory
92
Patent #:
6215705
Issue Dt:
04/10/2001
Application #:
09501448
Filing Dt:
02/10/2000
Title:
Simultaneous program, program-verify scheme
93
Patent #:
6348379
Issue Dt:
02/19/2002
Application #:
09502153
Filing Dt:
02/11/2000
Title:
Method of forming self-aligned contacts using consumable spacers
94
Patent #:
6420752
Issue Dt:
07/16/2002
Application #:
09502163
Filing Dt:
02/11/2000
Title:
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
95
Patent #:
6682978
Issue Dt:
01/27/2004
Application #:
09504087
Filing Dt:
02/15/2000
Title:
INTEGRATED CIRCUIT HAVING INCREASED GATE COUPLING CAPACITANCE
96
Patent #:
6205057
Issue Dt:
03/20/2001
Application #:
09504558
Filing Dt:
02/15/2000
Title:
System and method for detecting flash memory threshold voltages
97
Patent #:
6266281
Issue Dt:
07/24/2001
Application #:
09504695
Filing Dt:
02/16/2000
Title:
Method of erasing non-volatile memory cells
98
Patent #:
6215702
Issue Dt:
04/10/2001
Application #:
09504696
Filing Dt:
02/16/2000
Title:
Method of maintaining constant erasing speeds for non-volatile memory cells
99
Patent #:
6243300
Issue Dt:
06/05/2001
Application #:
09505259
Filing Dt:
02/16/2000
Title:
Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
100
Patent #:
6455888
Issue Dt:
09/24/2002
Application #:
09506298
Filing Dt:
02/17/2000
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
Assignor
1
BARCLAYS BANK PLC
Exec Dt:
03/12/2015
Assignees
1
SPANSION LLC
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
2
SPANSION INC.
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
3
SPANSION TECHNOLOGY LLC
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
Correspondence name and address
WILSON SONSINI GOODRICH & ROSATI
650 PAGE MILL ROAD
PALO ALTO, CA 94304

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