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Reel/Frame:035201/0159   Pages: 226
Recorded: 03/13/2015
Attorney Dkt #:3483.276
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 1788
Page 6 of 18
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1
Patent #:
6506640
Issue Dt:
01/14/2003
Application #:
09667686
Filing Dt:
09/22/2000
Title:
MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH
2
Patent #:
6324108
Issue Dt:
11/27/2001
Application #:
09667891
Filing Dt:
09/22/2000
Title:
Application of external voltage during array VT testing
3
Patent #:
6438041
Issue Dt:
08/20/2002
Application #:
09668100
Filing Dt:
09/22/2000
Title:
NEGATIVE VOLTAGE REGULATION
4
Patent #:
6391730
Issue Dt:
05/21/2002
Application #:
09670229
Filing Dt:
09/25/2000
Title:
PROCESS FOR FABRICATING SHALLOW POCKET REGIONS IN A NON-VOLATILE SEMICONDUCTOR DEVICE
5
Patent #:
6400633
Issue Dt:
06/04/2002
Application #:
09675372
Filing Dt:
09/29/2000
Title:
POWER-SAVING MODES FOR MEMORIES
6
Patent #:
6288951
Issue Dt:
09/11/2001
Application #:
09675940
Filing Dt:
09/29/2000
Title:
Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider
7
Patent #:
6813735
Issue Dt:
11/02/2004
Application #:
09676623
Filing Dt:
10/02/2000
Title:
I/O BASED COLUMN REDUNDANCY FOR VIRTUAL GROUND WITH 2-BIT CELL FLASH MEMORY
8
Patent #:
6310805
Issue Dt:
10/30/2001
Application #:
09676902
Filing Dt:
10/02/2000
Title:
Architecture for a dual-bank page mode memory with redundancy
9
Patent #:
6400638
Issue Dt:
06/04/2002
Application #:
09680344
Filing Dt:
10/05/2000
Title:
Wordline driver for flash memory read mode
10
Patent #:
6501681
Issue Dt:
12/31/2002
Application #:
09684694
Filing Dt:
10/04/2000
Title:
USING A LOW DRAIN BIAS DURING ERASE VERIFY TO ENSURE COMPLETE REMOVAL OF RESIDUAL CHARGE IN THE NITRIDE IN SONOS NON-VOLATILE MEMORIES
11
Patent #:
6271087
Issue Dt:
08/07/2001
Application #:
09685968
Filing Dt:
10/10/2000
Title:
Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects
12
Patent #:
6482699
Issue Dt:
11/19/2002
Application #:
09685972
Filing Dt:
10/10/2000
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS USING DECOUPLED LOCAL INTERCONNECT PROCESS
13
Patent #:
6477083
Issue Dt:
11/05/2002
Application #:
09686685
Filing Dt:
10/11/2000
Title:
SELECT TRANSISTOR ARCHITECTURE FOR A VIRTUAL GROUND NON-VOLATILE MEMORY CELL ARRAY
14
Patent #:
6366501
Issue Dt:
04/02/2002
Application #:
09686686
Filing Dt:
10/11/2000
Title:
Selective erasure of a non-volatile memory cell of a flash memory device
15
Patent #:
6349062
Issue Dt:
02/19/2002
Application #:
09686693
Filing Dt:
10/11/2000
Title:
Selective erasure of a non-volatile memory cell of a flash memory device
16
Patent #:
6537881
Issue Dt:
03/25/2003
Application #:
09688504
Filing Dt:
10/16/2000
Title:
PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
17
Patent #:
6583479
Issue Dt:
06/24/2003
Application #:
09688936
Filing Dt:
10/16/2000
Title:
SIDEWALL NROM AND METHOD OF MANUFACTURE THEREOF FOR NON-VOLATILE MEMORY CELLS
18
Patent #:
6373742
Issue Dt:
04/16/2002
Application #:
09689036
Filing Dt:
10/12/2000
Title:
Two side decoding of a memory array
19
Patent #:
6566252
Issue Dt:
05/20/2003
Application #:
09689144
Filing Dt:
10/11/2000
Title:
METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS AND DEVICE THEREBY FORMED
20
Patent #:
6567312
Issue Dt:
05/20/2003
Application #:
09689714
Filing Dt:
10/13/2000
Title:
A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A CHARGE STORING INSULATION FILM AND DATA HOLDING METHOD THEREFOR
21
Patent #:
6347052
Issue Dt:
02/12/2002
Application #:
09690554
Filing Dt:
10/17/2000
Title:
Word line decoding architecture in a flash memory
22
Patent #:
6537866
Issue Dt:
03/25/2003
Application #:
09691643
Filing Dt:
10/18/2000
Title:
METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE
23
Patent #:
6252803
Issue Dt:
06/26/2001
Application #:
09692881
Filing Dt:
10/23/2000
Title:
Automatic program disturb with intelligent soft programming for flash cells
24
Patent #:
6452840
Issue Dt:
09/17/2002
Application #:
09693649
Filing Dt:
10/21/2000
Title:
FEEDBACK METHOD TO OPTIMIZE ELECTRIC FIELD DURING CHANNEL ERASE OF FLASH MEMORY DEVICES
25
Patent #:
6233175
Issue Dt:
05/15/2001
Application #:
09693650
Filing Dt:
10/21/2000
Title:
Self-limiting multi-level programming states
26
Patent #:
6363014
Issue Dt:
03/26/2002
Application #:
09694688
Filing Dt:
10/23/2000
Title:
Low column leakage NOR flash array - single cell implementation
27
Patent #:
6269023
Issue Dt:
07/31/2001
Application #:
09694729
Filing Dt:
10/23/2000
Title:
Method of programming a non-volatile memory cell using a current limiter
28
Patent #:
6292425
Issue Dt:
09/18/2001
Application #:
09696652
Filing Dt:
10/25/2000
Title:
Power saving on the fly during reading of data from a memory device
29
Patent #:
6331952
Issue Dt:
12/18/2001
Application #:
09697810
Filing Dt:
10/26/2000
Title:
Positive gate erasure for non-volatile memory cells
30
Patent #:
6331953
Issue Dt:
12/18/2001
Application #:
09697813
Filing Dt:
10/26/2000
Title:
Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
31
Patent #:
6490205
Issue Dt:
12/03/2002
Application #:
09697814
Filing Dt:
10/26/2000
Title:
METHOD OF ERASING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
32
Patent #:
6438031
Issue Dt:
08/20/2002
Application #:
09697815
Filing Dt:
10/26/2000
Title:
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
33
Patent #:
6515344
Issue Dt:
02/04/2003
Application #:
09698485
Filing Dt:
10/30/2000
Title:
THIN OXIDE ANTI-FUSE
34
Patent #:
6507527
Issue Dt:
01/14/2003
Application #:
09698614
Filing Dt:
10/27/2000
Title:
MEMORY LINE DISCHARGE BEFORE SENSING
35
Patent #:
6500768
Issue Dt:
12/31/2002
Application #:
09699531
Filing Dt:
10/30/2000
Title:
METHOD FOR SELECTIVE REMOVAL OF ONO LAYER
36
Patent #:
6653189
Issue Dt:
11/25/2003
Application #:
09699711
Filing Dt:
10/30/2000
Title:
SOURCE SIDE BORON IMPLANT AND DRAIN SIDE MDD IMPLANT FOR DEEP SUB 0.18 MICRON FLASH MEMORY
37
Patent #:
6524914
Issue Dt:
02/25/2003
Application #:
09699972
Filing Dt:
10/30/2000
Title:
SOURCE SIDE BORON IMPLANTING AND DIFFUSING DEVICE ARCHITECTURE FOR DEEP SUB 0.18 MICRON FLASH MEMORY
38
Patent #:
6440789
Issue Dt:
08/27/2002
Application #:
09704026
Filing Dt:
11/01/2000
Title:
PHOTORESIST SPACER PROCESS SIMPLIFICATION TO ELIMINATE THE STANDARD POLYSILICON OR OXIDE SPACER PROCESS FOR FLASH MEMORY CIRCUITS
39
Patent #:
6277690
Issue Dt:
08/21/2001
Application #:
09708982
Filing Dt:
11/01/2000
Title:
Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant
40
Patent #:
6693009
Issue Dt:
02/17/2004
Application #:
09713390
Filing Dt:
11/15/2000
Title:
FLASH MEMORY CELL WITH MINIMIZED FLOATING GATE TO DRAIN/SOURCE OVERLAP FOR MINIMIZING CHARGE LEAKAGE
41
Patent #:
6306707
Issue Dt:
10/23/2001
Application #:
09716659
Filing Dt:
11/20/2000
Title:
Double layer hard mask process to improve oxide quality for non-volatile flash memory products
42
Patent #:
6331951
Issue Dt:
12/18/2001
Application #:
09717550
Filing Dt:
11/21/2000
Title:
Method and system for embedded chip erase verification
43
Patent #:
6593606
Issue Dt:
07/15/2003
Application #:
09718771
Filing Dt:
11/22/2000
Title:
STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
44
Patent #:
6472898
Issue Dt:
10/29/2002
Application #:
09718986
Filing Dt:
11/22/2000
Title:
METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR MEMORY DEVICE
45
Patent #:
6538270
Issue Dt:
03/25/2003
Application #:
09721031
Filing Dt:
11/22/2000
Title:
STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
46
Patent #:
6417081
Issue Dt:
07/09/2002
Application #:
09721066
Filing Dt:
11/22/2000
Title:
PROCESS FOR REDUCTION OF CAPACITANCE OF A BITLINE FOR A NON-VOLATILE MEMORY CELL
47
Patent #:
6324099
Issue Dt:
11/27/2001
Application #:
09721656
Filing Dt:
11/27/2000
Title:
2-Bit/cell type nonvolatile semiconductor memory
48
Patent #:
6465306
Issue Dt:
10/15/2002
Application #:
09723635
Filing Dt:
11/28/2000
Title:
SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
49
Patent #:
6468865
Issue Dt:
10/22/2002
Application #:
09723653
Filing Dt:
11/28/2000
Title:
METHOD OF SIMULTANEOUS FORMATION OF BITLINE ISOLATION AND PERIPHEY OXIDE
50
Patent #:
6622230
Issue Dt:
09/16/2003
Application #:
09724675
Filing Dt:
11/28/2000
Title:
MULTI-SET BLOCK ERASE
51
Patent #:
6413820
Issue Dt:
07/02/2002
Application #:
09725843
Filing Dt:
11/30/2000
Publication #:
US20010015456
Pub Dt:
08/23/2001
Title:
METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
52
Patent #:
6545912
Issue Dt:
04/08/2003
Application #:
09727656
Filing Dt:
11/30/2000
Title:
ERASE VERIFY MODE TO EVALUATE NEGATIVE VT'S
53
Patent #:
6969654
Issue Dt:
11/29/2005
Application #:
09727714
Filing Dt:
11/28/2000
Title:
FLASH NVROM DEVICES WITH UV CHARGE IMMUNITY
54
Patent #:
7012008
Issue Dt:
03/14/2006
Application #:
09728554
Filing Dt:
12/01/2000
Title:
DUAL SPACER PROCESS FOR NON-VOLATILE MEMORY DEVICES
55
Patent #:
6463003
Issue Dt:
10/08/2002
Application #:
09729388
Filing Dt:
12/04/2000
Publication #:
US20010050874
Pub Dt:
12/13/2001
Title:
POWER SAVING SCHEME FOR BURST MODE IMPLEMENTATION DURING READING OF DATA FROM A MEMORY DEVICE
56
Patent #:
6785856
Issue Dt:
08/31/2004
Application #:
09732616
Filing Dt:
12/07/2000
Title:
INTERNAL SELF-TEST CIRCUIT FOR A MEMORY ARRAY
57
Patent #:
6684353
Issue Dt:
01/27/2004
Application #:
09733252
Filing Dt:
12/07/2000
Title:
RELIABILITY MONITOR FOR A MEMORY ARRAY
58
Patent #:
6468861
Issue Dt:
10/22/2002
Application #:
09738760
Filing Dt:
12/18/2000
Publication #:
US20010021133
Pub Dt:
09/13/2001
Title:
METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
59
Patent #:
6596591
Issue Dt:
07/22/2003
Application #:
09739733
Filing Dt:
12/18/2000
Title:
METHODS TO FORM REDUCED DIMENSION BIT-LINE ISOLATION IN THE MANUFACTURE OF NON-VOLATILE MEMORY DEVICES
60
Patent #:
6449190
Issue Dt:
09/10/2002
Application #:
09764965
Filing Dt:
01/17/2001
Title:
ADAPTIVE REFERENCE CELLS FOR A MEMORY DEVICE
61
Patent #:
6459625
Issue Dt:
10/01/2002
Application #:
09767341
Filing Dt:
01/23/2001
Title:
THREE METAL PROCESS FOR OPTIMIZING LAYOUT DENSITY
62
Patent #:
6445030
Issue Dt:
09/03/2002
Application #:
09772600
Filing Dt:
01/30/2001
Title:
FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION
63
Patent #:
6410949
Issue Dt:
06/25/2002
Application #:
09774327
Filing Dt:
01/31/2001
Publication #:
US20010005633
Pub Dt:
06/28/2001
Title:
FLASH MEMORY DEVICE WITH MONITOR STRUCTURE FOR MONITORING SECOND GATE OVER-ETCH
64
Patent #:
6275424
Issue Dt:
08/14/2001
Application #:
09774509
Filing Dt:
01/31/2001
Title:
Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
65
Patent #:
6727195
Issue Dt:
04/27/2004
Application #:
09777457
Filing Dt:
02/06/2001
Publication #:
US20010045648
Pub Dt:
11/29/2001
Title:
METHOD AND SYSTEM FOR DECREASING THE SPACES BETWEEN WORDLINES
66
Patent #:
6444539
Issue Dt:
09/03/2002
Application #:
09784892
Filing Dt:
02/15/2001
Title:
METHOD FOR PRODUCING A SHALLOW TRENCH ISOLATION FILLED WITH THERMAL OXIDE
67
Patent #:
6489253
Issue Dt:
12/03/2002
Application #:
09788045
Filing Dt:
02/16/2001
Title:
METHOD OF FORMING A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-UM FLASH MEMORY TECHNOLOGY AND SEMICONDUCTOR DEVICE THEREBY FORMED
68
Patent #:
6614683
Issue Dt:
09/02/2003
Application #:
09794480
Filing Dt:
02/26/2001
Title:
ASCENDING STAIRCASE READ TECHNIQUE FOR A MULTILEVEL CELL NAND FLASH MEMORY DEVICE
69
Patent #:
6344994
Issue Dt:
02/05/2002
Application #:
09795849
Filing Dt:
02/28/2001
Title:
Data retention characteristics as a result of high temperature bake
70
Patent #:
6442074
Issue Dt:
08/27/2002
Application #:
09795854
Filing Dt:
02/28/2001
Title:
TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE
71
Patent #:
6307784
Issue Dt:
10/23/2001
Application #:
09795856
Filing Dt:
02/28/2001
Title:
Negative gate erase
72
Patent #:
6493261
Issue Dt:
12/10/2002
Application #:
09795865
Filing Dt:
02/28/2001
Title:
SINGLE BIT ARRAY EDGES
73
Patent #:
6456533
Issue Dt:
09/24/2002
Application #:
09796282
Filing Dt:
02/28/2001
Publication #:
US20020159293
Pub Dt:
10/31/2002
Title:
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
74
Patent #:
6528390
Issue Dt:
03/04/2003
Application #:
09798667
Filing Dt:
03/02/2001
Publication #:
US20020132446
Pub Dt:
09/19/2002
Title:
PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
75
Patent #:
6306713
Issue Dt:
10/23/2001
Application #:
09799469
Filing Dt:
03/05/2001
Title:
Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
76
Patent #:
6534363
Issue Dt:
03/18/2003
Application #:
09803400
Filing Dt:
03/12/2001
Publication #:
US20020127799
Pub Dt:
09/12/2002
Title:
HIGH VOLTAGE OXIDATION METHOD FOR HIGHLY RELIABLE FLASH MEMORY DEVICES
77
Patent #:
7217652
Issue Dt:
05/15/2007
Application #:
09805273
Filing Dt:
03/13/2001
Title:
A METHOD OF FORMING HIGHLY CONDUCTIVE SEMICONDUCTOR STRUCTURES VIA PLASMA ETCH
78
Patent #:
6627526
Issue Dt:
09/30/2003
Application #:
09805287
Filing Dt:
03/13/2001
Title:
METHOD FOR FABRICATING A CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR DEVICE
79
Patent #:
6713809
Issue Dt:
03/30/2004
Application #:
09809969
Filing Dt:
03/16/2001
Title:
DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
80
Patent #:
6573140
Issue Dt:
06/03/2003
Application #:
09810155
Filing Dt:
03/16/2001
Title:
PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
81
Patent #:
6376309
Issue Dt:
04/23/2002
Application #:
09811288
Filing Dt:
03/16/2001
Publication #:
US20010016386
Pub Dt:
08/23/2001
Title:
Method for reduced gate aspect ratio to improve gap-fill after spacer etch
82
Patent #:
6376312
Issue Dt:
04/23/2002
Application #:
09817628
Filing Dt:
03/26/2001
Title:
FORMATION OF NON-VOLATILE MEMORY DEVICE COMPRISED OF AN ARRAY OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURES
83
Patent #:
6480420
Issue Dt:
11/12/2002
Application #:
09818652
Filing Dt:
03/28/2001
Publication #:
US20020031009
Pub Dt:
03/14/2002
Title:
SEMICONDUCTOR MEMORY DEVICE HAVING SOURCE AREAS OF MEMORY CELLS SUPPLIED WITH A COMMON VOLTAGE
84
Patent #:
6459628
Issue Dt:
10/01/2002
Application #:
09824166
Filing Dt:
04/02/2001
Title:
SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
85
Patent #:
6337246
Issue Dt:
01/08/2002
Application #:
09824841
Filing Dt:
04/02/2001
Title:
Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
86
Patent #:
6838869
Issue Dt:
01/04/2005
Application #:
09825027
Filing Dt:
04/02/2001
Title:
CLOCKED BASED METHOD AND DEVICES FOR MEASURING VOLTAGE-VARIABLE CAPACITANCES AND OTHER ON-CHIP PARAMETERS
87
Patent #:
6493266
Issue Dt:
12/10/2002
Application #:
09829193
Filing Dt:
04/09/2001
Publication #:
US20030021155
Pub Dt:
01/30/2003
Title:
SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY
88
Patent #:
6621761
Issue Dt:
09/16/2003
Application #:
09829518
Filing Dt:
04/09/2001
Publication #:
US20020012278
Pub Dt:
01/31/2002
Title:
BURST ARCHITECTURE FOR A FLASH MEMORY
89
Patent #:
6396749
Issue Dt:
05/28/2002
Application #:
09829657
Filing Dt:
04/10/2001
Publication #:
US20010048613
Pub Dt:
12/06/2001
Title:
DUAL-PORTED CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
90
Patent #:
6680507
Issue Dt:
01/20/2004
Application #:
09833307
Filing Dt:
04/11/2001
Publication #:
US20020048881
Pub Dt:
04/25/2002
Title:
DUAL BIT ISOLATION SCHEME FOR FLASH MEMORY DEVICES HAVING POLYSILICON FLOATING GATES
91
Patent #:
6455373
Issue Dt:
09/24/2002
Application #:
09834419
Filing Dt:
04/12/2001
Title:
SEMICONDUCTOR DEVICE HAVING GATE EDGES PROTECTED FROM CHARGE GAIN/LOSS
92
Patent #:
6420224
Issue Dt:
07/16/2002
Application #:
09836064
Filing Dt:
04/16/2001
Publication #:
US20010022405
Pub Dt:
09/20/2001
Title:
STEPPER ALIGNMENT MARK FORMATION WITH DUAL FIELD OXIDE PROCESS
93
Patent #:
6966016
Issue Dt:
11/15/2005
Application #:
09836065
Filing Dt:
04/16/2001
Publication #:
US20020152435
Pub Dt:
10/17/2002
Title:
SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
94
Patent #:
6400608
Issue Dt:
06/04/2002
Application #:
09842288
Filing Dt:
04/25/2001
Title:
ACCURATE VERIFY APPARATUS AND METHOD FOR NOR FLASH MEMORY CELLS IN THE PRESENCE OF HIGH COLUMN LEAKAGE
95
Patent #:
6514822
Issue Dt:
02/04/2003
Application #:
09844692
Filing Dt:
04/27/2001
Publication #:
US20020158284
Pub Dt:
10/31/2002
Title:
METHOD AND SYSTEM FOR REDUCING THINNING OF FIELD ISOLATION STRUCTURES IN A FLASH MEMORY DEVICE
96
Patent #:
6509229
Issue Dt:
01/21/2003
Application #:
09850484
Filing Dt:
05/07/2001
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS USING CONSUMABLE SPACERS
97
Patent #:
6438037
Issue Dt:
08/20/2002
Application #:
09851773
Filing Dt:
05/09/2001
Title:
THRESHOLD VOLTAGE COMPACTING FOR NON-VOLATILE SEMICONDUCTOR MEMORY DESIGNS
98
Patent #:
6510085
Issue Dt:
01/21/2003
Application #:
09861031
Filing Dt:
05/18/2001
Title:
METHOD OF CHANNEL HOT ELECTRON PROGRAMMING FOR SHORT CHANNEL NOR FLASH ARRAYS
99
Patent #:
6515902
Issue Dt:
02/04/2003
Application #:
09873643
Filing Dt:
06/04/2001
Title:
METHOD AND APPARATUS FOR BOOSTING BITLINES FOR LOW VCC READ
100
Patent #:
6381163
Issue Dt:
04/30/2002
Application #:
09873927
Filing Dt:
06/04/2001
Title:
METHODS AND APPARATUS FOR READING A CAM CELL USING BOOSTED AND REGULATED GATE VOLTAGE
Assignor
1
BARCLAYS BANK PLC
Exec Dt:
03/12/2015
Assignees
1
SPANSION LLC
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
2
SPANSION INC.
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
3
SPANSION TECHNOLOGY LLC
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
Correspondence name and address
WILSON SONSINI GOODRICH & ROSATI
650 PAGE MILL ROAD
PALO ALTO, CA 94304

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