USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	035201/0159			Pages:	226
		Recorded:	03/13/2015
Attorney Dkt #:	3483.276
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 1788
Page 7 of 18
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Patent #:	6617179	Issue Dt:	09/09/2003	Application #:	09875056	Filing Dt:	06/05/2001
Title:	METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE

Patent #:	6509202	Issue Dt:	01/21/2003	Application #:	09875073	Filing Dt:	06/05/2001
Title:	METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE

Patent #:	6436778	Issue Dt:	08/20/2002	Application #:	09879738	Filing Dt:	06/12/2001
Title:	NOVEL RE-OXIDATION APPROACH TO IMPROVE PERIPHERAL GATE OXIDE INTEGRITY IN A TUNNEL NITRIDE OXIDATION PROCESS

Patent #:	6618290	Issue Dt:	09/09/2003	Application #:	09880366	Filing Dt:	06/13/2001
Title:	METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A BAKING PROCESS

Patent #:	6459618	Issue Dt:	10/01/2002	Application #:	09880367	Filing Dt:	06/13/2001
Title:	METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A DRAIN BIAS

Patent #:	6399984	Issue Dt:	06/04/2002	Application #:	09882242	Filing Dt:	06/15/2001
Title:	SPECIES IMPLANTATION FOR MINIMIZING INTERFACE DEFECT DENSITY IN FLASH MEMORY DEVICES

Patent #:	6573151	Issue Dt:	06/03/2003	Application #:	09884204	Filing Dt:	06/19/2001
Title:	METHOD OF FORMING ZERO MARKS

Patent #:	6456531	Issue Dt:	09/24/2002	Application #:	09884402	Filing Dt:	06/19/2001
Title:	METHOD OF DRAIN AVALANCHE PROGRAMMING OF A NON-VOLATILE MEMORY CELL

Patent #:	6456536	Issue Dt:	09/24/2002	Application #:	09884409	Filing Dt:	06/19/2001
Title:	METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS

Patent #:	6449188	Issue Dt:	09/10/2002	Application #:	09884565	Filing Dt:	06/19/2001
Title:	LOW COLUMN LEAKAGE NOR FLASH ARRAY-DOUBLE CELL IMPLEMENTATION

Patent #:	6370061	Issue Dt:	04/09/2002	Application #:	09884583	Filing Dt:	06/19/2001
Title:	Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells

Patent #:	7125763	Issue Dt:	10/24/2006	Application #:	09885426	Filing Dt:	06/19/2001
Title:	SILICIDED BURIED BITLINE PROCESS FOR A NON-VOLATILE MEMORY CELL

Patent #:	6465303	Issue Dt:	10/15/2002	Application #:	09885490	Filing Dt:	06/20/2001
Title:	METHOD OF MANUFACTURING SPACER ETCH MASK FOR SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE NONVOLATILE MEMORY

Patent #:	6512701	Issue Dt:	01/28/2003	Application #:	09886861	Filing Dt:	06/21/2001
Title:	ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH

Patent #:	6900085	Issue Dt:	05/31/2005	Application #:	09891885	Filing Dt:	06/26/2001
Publication #:	US20020195663	Pub Dt:	12/26/2002
Title:	ESD IMPLANT FOLLOWING SPACER DEPOSITION

Patent #:	6633949	Issue Dt:	10/14/2003	Application #:	09892431	Filing Dt:	06/26/2001
Publication #:	US20020010828	Pub Dt:	01/24/2002
Title:	BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE

Patent #:	6525368	Issue Dt:	02/25/2003	Application #:	09892685	Filing Dt:	06/27/2001
Title:	HIGH DENSITY FLASH EEPROM ARRAY WITH SOURCE SIDE INJECTION

Patent #:	6541816	Issue Dt:	04/01/2003	Application #:	09893026	Filing Dt:	06/27/2001
Publication #:	US20020063277	Pub Dt:	05/30/2002
Title:	PLANAR STRUCTURE FOR NON-VOLATILE MEMORY DEVICES

Patent #:	6436768	Issue Dt:	08/20/2002	Application #:	09893279	Filing Dt:	06/27/2001
Title:	SOURCE DRAIN IMPLANT DURING ONO FORMATION FOR IMPROVED ISOLATION OF SONOS DEVICES

Patent #:	6487121	Issue Dt:	11/26/2002	Application #:	09899721	Filing Dt:	07/05/2001
Title:	METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A VERTICAL ELECTRIC FIELD

Patent #:	6519182	Issue Dt:	02/11/2003	Application #:	09902332	Filing Dt:	07/10/2001
Title:	USING HOT CARRIER INJECTION TO CONTROL OVER-PROGRAMMING IN A NON-VOLATILE MEMORY CELL HAVING AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE

Patent #:	6933554	Issue Dt:	08/23/2005	Application #:	09904042	Filing Dt:	07/11/2001
Title:	RECESSED TUNNEL OXIDE PROFILE FOR IMPROVED RELIABILITY IN NAND DEVICES

Patent #:	6589804	Issue Dt:	07/08/2003	Application #:	09904089	Filing Dt:	07/12/2001
Title:	OXIDE/NITRIDE OR OXIDE/NITRIDE/OXIDE THICKNESS MEASUREMENT USING SCATTEROMETRY

Patent #:	6486682	Issue Dt:	11/26/2002	Application #:	09904736	Filing Dt:	07/13/2001
Title:	DETERMINATION OF DIELECTRIC CONSTANTS OF THIN DIELECTRIC MATERIALS IN A MOS (METAL OXIDE SEMICONDUCTOR) STACK

Patent #:	6665777	Issue Dt:	12/16/2003	Application #:	09912834	Filing Dt:	07/25/2001
Publication #:	US20020029800	Pub Dt:	03/14/2002
Title:	MULTIPLE BLOCK SEQUENTIAL MEMORY MANAGEMENT

Patent #:	6782440	Issue Dt:	08/24/2004	Application #:	09912870	Filing Dt:	07/25/2001
Publication #:	US20020016879	Pub Dt:	02/07/2002
Title:	RESOURCE LOCKING AND THREAD SYNCHRONIZATION IN A MULTIPROCESSOR ENVIRONMENT

Patent #:	6715059	Issue Dt:	03/30/2004	Application #:	09912898	Filing Dt:	07/25/2001
Publication #:	US20020016900	Pub Dt:	02/07/2002
Title:	METHODS AND SYSTEMS FOR A SHARED MEMORY UNIT WITH EXTENDABLE FUNCTIONS

Patent #:	6675277	Issue Dt:	01/06/2004	Application #:	09912954	Filing Dt:	07/25/2001
Publication #:	US20020016899	Pub Dt:	02/07/2002
Title:	DEMAND USABLE ADAPTER MEMORY ACCESS MANAGEMENT

Patent #:	6535424	Issue Dt:	03/18/2003	Application #:	09915018	Filing Dt:	07/25/2001
Publication #:	US20030021152	Pub Dt:	01/30/2003
Title:	VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES

Patent #:	6892298	Issue Dt:	05/10/2005	Application #:	09915109	Filing Dt:	07/25/2001
Publication #:	US20020013868	Pub Dt:	01/31/2002
Title:	LOAD/STORE MICROPACKET HANDLING SYSTEM

Patent #:	6525959	Issue Dt:	02/25/2003	Application #:	09917178	Filing Dt:	07/30/2001
Title:	NOR ARRAY WITH BURIED TRENCH SOURCE LINE

Patent #:	6541338	Issue Dt:	04/01/2003	Application #:	09917182	Filing Dt:	07/30/2001
Publication #:	US20030022440	Pub Dt:	01/30/2003
Title:	LOW DEFECT DENSITY PROCESS FOR DEEP SUB-0.18UM FLASH MEMORY TECHNOLOGIES

Patent #:	6888157	Issue Dt:	05/03/2005	Application #:	09917440	Filing Dt:	07/27/2001
Title:	N-GATE/N-SUBSTRATE OR P-GATE/P-SUBSTRATE CAPACITOR TO CHARACTERIZE POLYSILICON GATE DEPLETION EVALUATION

Patent #:	6504757	Issue Dt:	01/07/2003	Application #:	09922415	Filing Dt:	08/03/2001
Title:	DOUBLE BOOSTING SCHEME FOR NAND TO IMPROVE PROGRAM INHIBIT CHARACTERISTICS

Patent #:	6472327	Issue Dt:	10/29/2002	Application #:	09925205	Filing Dt:	08/08/2001
Publication #:	US20020028583	Pub Dt:	03/07/2002
Title:	METHOD AND SYSTEM FOR ETCHING TUNNEL OXIDE TO REDUCE UNDERCUTTING DURING MEMORY ARRAY FABRICATION

Patent #:	6709927	Issue Dt:	03/23/2004	Application #:	09927134	Filing Dt:	08/10/2001
Title:	PROCESS FOR TREATING ONO DIELECTRIC FILM OF A FLOATING GATE MEMORY CELL

Patent #:	6559500	Issue Dt:	05/06/2003	Application #:	09927387	Filing Dt:	08/13/2001
Publication #:	US20030067030	Pub Dt:	04/10/2003
Title:	NON-VOLATILE SEMICONDUCTOR MEMORY AND ITS DRIVING METHOD

Patent #:	6525969	Issue Dt:	02/25/2003	Application #:	09928059	Filing Dt:	08/10/2001
Title:	DECODER APPARATUS AND METHODS FOR PRE-CHARGING BIT LINES

Patent #:	6979619	Issue Dt:	12/27/2005	Application #:	09941370	Filing Dt:	08/28/2001
Title:	FLASH MEMORY DEVICE AND A METHOD OF FABRICATION THEREOF

Patent #:	6492677	Issue Dt:	12/10/2002	Application #:	09963632	Filing Dt:	09/27/2001
Publication #:	US20020060365	Pub Dt:	05/23/2002
Title:	NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS THEREOF

Patent #:	6440797	Issue Dt:	08/27/2002	Application #:	09966702	Filing Dt:	09/28/2001
Title:	NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN A FABRICATION OF SONOS FLASH MEMORY

Patent #:	6645801	Issue Dt:	11/11/2003	Application #:	09968456	Filing Dt:	10/01/2001
Title:	SALICIDED GATE FOR VIRTUAL GROUND ARRAYS

Patent #:	6566194	Issue Dt:	05/20/2003	Application #:	09968465	Filing Dt:	10/01/2001
Publication #:	US20030085417	Pub Dt:	05/08/2003
Title:	SALICIDED GATE FOR VIRTUAL GROUND ARRAYS

Patent #:	6469939	Issue Dt:	10/22/2002	Application #:	09969572	Filing Dt:	10/01/2001
Title:	FLASH MEMORY DEVICE WITH INCREASE OF EFFICIENCY DURING AN APDE (AUTOMATIC PROGRAM DISTURB AFTER ERASE) PROCESS

Patent #:	6509232	Issue Dt:	01/21/2003	Application #:	09969573	Filing Dt:	10/01/2001
Title:	FORMATION OF STI (SHALLOW TRENCH ISOLATION) STRUCTURES WITHIN CORE AND PERIPHERY AREAS OF FLASH MEMORY DEVICE

Patent #:	6630384	Issue Dt:	10/07/2003	Application #:	09971483	Filing Dt:	10/05/2001
Title:	METHOD OF FABRICATING DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY

Patent #:	6664191	Issue Dt:	12/16/2003	Application #:	09973131	Filing Dt:	10/09/2001
Title:	NON SELF-ALIGNED SHALLOW TRENCH ISOLATION PROCESS WITH DISPOSABLE SPACE TO DEFINE SUB-LITHOGRAPHIC POLY SPACE

Patent #:	6642586	Issue Dt:	11/04/2003	Application #:	09973743	Filing Dt:	10/11/2001
Publication #:	US20020105037	Pub Dt:	08/08/2002
Title:	SEMICONDUCTOR MEMORY CAPABLE OF BEING DRIVEN AT LOW VOLTAGE AND ITS MANUFACTURE METHOD

Patent #:	6566736	Issue Dt:	05/20/2003	Application #:	09998624	Filing Dt:	11/30/2001
Title:	DIE SEAL FOR SEMICONDUCTOR DEVICE MOISTURE PROTECTION

Patent #:	6510082	Issue Dt:	01/21/2003	Application #:	09999869	Filing Dt:	10/23/2001
Title:	DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD

Patent #:	6620705	Issue Dt:	09/16/2003	Application #:	10006529	Filing Dt:	12/05/2001
Title:	NITRIDING PRETREATMENT OF ONO NITRIDE FOR OXIDE DEPOSITION

Patent #:	6858496	Issue Dt:	02/22/2005	Application #:	10010280	Filing Dt:	12/05/2001
Title:	OXIDIZING PRETREATMENT OF ONO LAYER FOR FLASH MEMORY

Patent #:	6525966	Issue Dt:	02/25/2003	Application #:	10010985	Filing Dt:	12/05/2001
Title:	METHOD AND APPARATUS FOR ADJUSTING ON-CHIP CURRENT REFERENCE FOR EEPROM SENSING

Patent #:	6700201	Issue Dt:	03/02/2004	Application #:	10013902	Filing Dt:	12/11/2001
Title:	REDUCTION OF SECTOR CONNECTING LINE CAPACITANCE USING STAGGERED METAL LINES

Patent #:	6654283	Issue Dt:	11/25/2003	Application #:	10013993	Filing Dt:	12/11/2001
Title:	FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING AND READING THEREOF

Patent #:	7002381	Issue Dt:	02/21/2006	Application #:	10015033	Filing Dt:	12/11/2001
Title:	SWITCHED-CAPACITOR CONTROLLER TO CONTROL THE RISE TIMES OF ON-CHIP GENERATED HIGH VOLTAGES

Patent #:	6731130	Issue Dt:	05/04/2004	Application #:	10017832	Filing Dt:	12/12/2001
Title:	METHOD OF DETERMINING GATE OXIDE THICKNESS OF AN OPERATIONAL MOSFET

Patent #:	6723605	Issue Dt:	04/20/2004	Application #:	10022292	Filing Dt:	12/15/2001
Title:	METHOD FOR MANUFACTURING MEMORY WITH HIGH CONDUCTIVITY BITLINE AND SHALLOW TRENCH ISOLATION INTEGRATION

Patent #:	6828199	Issue Dt:	12/07/2004	Application #:	10022798	Filing Dt:	12/20/2001
Publication #:	US20030119314	Pub Dt:	06/26/2003
Title:	MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE

Patent #:	6500713	Issue Dt:	12/31/2002	Application #:	10023349	Filing Dt:	12/20/2001
Title:	METHOD FOR REPAIRING DAMAGE TO CHARGE TRAPPING DIELECTRIC LAYER FROM BIT LINE IMPLANTATION

Patent #:	6653190	Issue Dt:	11/25/2003	Application #:	10023436	Filing Dt:	12/15/2001
Title:	FLASH MEMORY WITH CONTROLLED WORDLINE WIDTH

Patent #:	6639271	Issue Dt:	10/28/2003	Application #:	10027253	Filing Dt:	12/20/2001
Title:	FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME

Patent #:	6670669	Issue Dt:	12/30/2003	Application #:	10030117	Filing Dt:	01/23/2002
Title:	MULTIPLE-BIT NON-VOLATILE MEMORY UTILIZING NON-CONDUCTIVE CHARGE TRAPPING GATE

Patent #:	6566230	Issue Dt:	05/20/2003	Application #:	10032630	Filing Dt:	12/27/2001
Title:	SHALLOW TRENCH ISOLATION SPACER FOR WEFF IMPROVEMENT

Patent #:	6740926	Issue Dt:	05/25/2004	Application #:	10032646	Filing Dt:	12/27/2001
Title:	PLANAR TRANSISTOR STRUCTURE USING ISOLATION IMPLANTS FOR IMPROVED VSS RESISTANCE AND FOR PROCESS SIMPLIFICATION

Patent #:	6974995	Issue Dt:	12/13/2005	Application #:	10032757	Filing Dt:	12/27/2001
Title:	METHOD AND SYSTEM FOR FORMING DUAL GATE STRUCTURES IN A NONVOLATILE MEMORY USING A PROTECTIVE LAYER

Patent #:	6674138	Issue Dt:	01/06/2004	Application #:	10036757	Filing Dt:	12/31/2001
Title:	USE OF HIGH-K DIELECTRIC MATERIALS IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES

Patent #:	6496414	Issue Dt:	12/17/2002	Application #:	10043114	Filing Dt:	01/14/2002
Publication #:	US20020154542	Pub Dt:	10/24/2002
Title:	NONVOLATILE SEMICONDUCTOR MEMORY

Patent #:	6514830	Issue Dt:	02/04/2003	Application #:	10044510	Filing Dt:	01/11/2002
Title:	METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK

Patent #:	6809033	Issue Dt:	10/26/2004	Application #:	10045354	Filing Dt:	11/07/2001
Title:	INNOVATIVE METHOD OF HARD MASK REMOVAL

Patent #:	6515903	Issue Dt:	02/04/2003	Application #:	10050254	Filing Dt:	01/16/2002
Title:	NEGATIVE PUMP REGULATOR USING MOS CAPACITOR

Patent #:	6529412	Issue Dt:	03/04/2003	Application #:	10050257	Filing Dt:	01/16/2002
Title:	SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE

Patent #:	7057949	Issue Dt:	06/06/2006	Application #:	10050342	Filing Dt:	01/16/2002
Title:	METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS

Patent #:	6770938	Issue Dt:	08/03/2004	Application #:	10050394	Filing Dt:	01/16/2002
Title:	DIODE FABRICATION FOR ESD/EOS PROTECTION

Patent #:	6567303	Issue Dt:	05/20/2003	Application #:	10050483	Filing Dt:	01/16/2002
Title:	CHARGE INJECTION

Patent #:	6532175	Issue Dt:	03/11/2003	Application #:	10050650	Filing Dt:	01/16/2002
Title:	METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE

Patent #:	6574139	Issue Dt:	06/03/2003	Application #:	10052484	Filing Dt:	01/18/2002
Publication #:	US20030081458	Pub Dt:	05/01/2003
Title:	METHOD AND DEVICE FOR READING DUAL BIT MEMORY CELLS USING MULTIPLE REFERENCE CELLS WITH TWO SIDE READ

Patent #:	6852594	Issue Dt:	02/08/2005	Application #:	10053256	Filing Dt:	01/18/2002
Title:	TWO-STEP SOURCE SIDE IMPLANT FOR IMPROVING SOURCE RESISTANCE AND SHORT CHANNEL EFFECT IN DEEP SUB-0.18MUM FLASH MEMORY TECHNOLOGY

Patent #:	6611473	Issue Dt:	08/26/2003	Application #:	10061620	Filing Dt:	02/01/2002
Publication #:	US20020071331	Pub Dt:	06/13/2002
Title:	POWER-SAVING MODES FOR MEMORIES

Patent #:	6548336	Issue Dt:	04/15/2003	Application #:	10067765	Filing Dt:	02/08/2002
Publication #:	US20020072219	Pub Dt:	06/13/2002
Title:	PLANARIZATION OF A POLYSILICON LAYER SURFACE BY CHEMICAL MECHANICAL POLISH TO IMPROVE LITHOGRAPHY AND SILICIDE FORMATION

Patent #:	6614686	Issue Dt:	09/02/2003	Application #:	10069124	Filing Dt:	03/01/2002
Title:	NONVOLATILE MEMORY CIRCUIT FOR RECORDING MULTIPLE BIT INFORMATION

Patent #:	7015134	Issue Dt:	03/21/2006	Application #:	10079775	Filing Dt:	02/19/2002
Publication #:	US20020076931	Pub Dt:	06/20/2002
Title:	METHOD FOR REDUCING ANTI-REFLECTIVE COATING LAYER REMOVAL DURING REMOVAL OF PHOTORESIST

Patent #:	6461905	Issue Dt:	10/08/2002	Application #:	10081246	Filing Dt:	02/22/2002
Title:	DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS

Patent #:	6654285	Issue Dt:	11/25/2003	Application #:	10083789	Filing Dt:	02/27/2002
Title:	METHOD OF MATCHING CORE CELL AND REFERENCE CELL SOURCE RESISTANCES

Patent #:	6750520	Issue Dt:	06/15/2004	Application #:	10085023	Filing Dt:	03/01/2002
Publication #:	US20020084484	Pub Dt:	07/04/2002
Title:	SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURE THEREOF

Patent #:	6750103	Issue Dt:	06/15/2004	Application #:	10086112	Filing Dt:	02/27/2002
Title:	NROM CELL WITH N-LESS CHANNEL

Patent #:	6737703	Issue Dt:	05/18/2004	Application #:	10095512	Filing Dt:	03/12/2002
Title:	MEMORY ARRAY WITH BURIED BIT LINES

Patent #:	6768683	Issue Dt:	07/27/2004	Application #:	10095739	Filing Dt:	03/12/2002
Title:	LOW COLUMN LEAKAGE FLASH MEMORY ARRAY

Patent #:	6646914	Issue Dt:	11/11/2003	Application #:	10096313	Filing Dt:	03/12/2002
Title:	FLASH MEMORY ARRAY ARCHITECTURE HAVING STAGGERED METAL LINES

Patent #:	6781884	Issue Dt:	08/24/2004	Application #:	10096338	Filing Dt:	03/11/2002
Publication #:	US20030169623	Pub Dt:	09/11/2003
Title:	SYSTEM FOR SETTING MEMORY VOLTAGE THRESHOLD

Patent #:	6706576	Issue Dt:	03/16/2004	Application #:	10096741	Filing Dt:	03/14/2002
Title:	LASER THERMAL ANNEALING OF SILICON NITRIDE FOR INCREASED DENSITY AND ETCH SELECTIVITY

Patent #:	7096406	Issue Dt:	08/22/2006	Application #:	10097499	Filing Dt:	03/15/2002
Publication #:	US20030041299	Pub Dt:	02/27/2003
Title:	MEMORY CONTROLLER FOR MULTILEVEL CELL MEMORY

Patent #:	6642573	Issue Dt:	11/04/2003	Application #:	10097912	Filing Dt:	03/13/2002
Title:	USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES

Patent #:	6574149	Issue Dt:	06/03/2003	Application #:	10097924	Filing Dt:	03/15/2002
Publication #:	US20020093851	Pub Dt:	07/18/2002
Title:	SEMICONDUCTOR MEMORY AND ITS USAGE

Patent #:	6639844	Issue Dt:	10/28/2003	Application #:	10099499	Filing Dt:	03/13/2002
Title:	OVERERASE CORRECTION METHOD

Patent #:	6706595	Issue Dt:	03/16/2004	Application #:	10100485	Filing Dt:	03/14/2002
Publication #:	US20040014290	Pub Dt:	01/22/2004
Title:	HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS

Patent #:	6620717	Issue Dt:	09/16/2003	Application #:	10100487	Filing Dt:	03/14/2002
Title:	MEMORY WITH DISPOSABLE ARC FOR WORDLINE FORMATION

Patent #:	6590260	Issue Dt:	07/08/2003	Application #:	10103077	Filing Dt:	03/20/2002
Title:	MEMORY DEVICE HAVING IMPROVED PROGRAMMABILITY

Patent #:	6670616	Issue Dt:	12/30/2003	Application #:	10103557	Filing Dt:	03/22/2002
Publication #:	US20030052279	Pub Dt:	03/20/2003
Title:	ULTRAVIOLET-LIGHT IRRADIATION APPARATUS