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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10109235
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Filing Dt:
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03/27/2002
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Title:
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MEMORY WORDLINE HARD MASK
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Patent #:
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Issue Dt:
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11/12/2002
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10109516
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Filing Dt:
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03/27/2002
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Title:
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METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
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Patent #:
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Issue Dt:
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11/05/2002
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10109526
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Filing Dt:
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03/27/2002
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Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
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Issue Dt:
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07/15/2003
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10112976
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Filing Dt:
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03/28/2002
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Title:
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A TEST STRUCTURE APPARATUS FOR MEASURING STANDBY CURRENT IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/29/2004
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10113017
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Filing Dt:
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03/28/2002
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Title:
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METHOD OF DETERMINING LOCATION OF GATE OXIDE BREAKDOWN OF MOSFET BY MEASURING CURRENTS
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10113152
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Filing Dt:
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03/28/2002
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Title:
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METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL STRESS
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10113259
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Filing Dt:
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03/28/2002
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Title:
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METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL TRAPPING
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10117818
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Filing Dt:
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04/08/2002
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Title:
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PRECISION HIGH-K INTERGATE DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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07/13/2004
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Application #:
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10118363
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Filing Dt:
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04/08/2002
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Title:
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STACKED POLYSILICON LAYER FOR BORON PENETRATION INHIBITION
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Patent #:
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03/02/2004
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Application #:
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10119273
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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REFRESH SCHEME FOR DYNAMIC PAGE PROGRAMMING
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10119366
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Filing Dt:
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04/08/2002
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Title:
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ERASE METHOD FOR A DUAL BIT MEMORY CELL
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Issue Dt:
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02/10/2004
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Application #:
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10119391
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Filing Dt:
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04/08/2002
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Title:
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ALGORITHM DYNAMIC REFERENCE PROGRAMMING
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10120116
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Filing Dt:
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04/09/2002
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Title:
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ISOLATION TRENCH FILL PROCESS
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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10121140
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Filing Dt:
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04/11/2002
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Title:
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METHODS AND SYSTEMS FOR FLASH MEMORY TUNNEL OXIDE RELIABILITY TESTING
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Issue Dt:
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11/23/2004
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10126193
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Filing Dt:
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04/19/2002
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Title:
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METHOD OF DETECTING AND DISTINGUISHING STACK GATE EDGE DEFECTS AT THE SOURCE OR DRAIN JUNCTION
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10126207
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Filing Dt:
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04/19/2002
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Title:
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USING A FIRST LINER LAYER AS A SPACER IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10126280
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Filing Dt:
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04/19/2002
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Title:
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MEMORY MANUFACTURING PROCESS USING DISPOSABLE ARC FOR WORDLINE FORMATION
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10126326
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Filing Dt:
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04/19/2002
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Title:
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RELACS SHRINK METHOD APPLIED FOR SINGLE PRINT RESIST MASK FOR LDD OR BURIED BITLINE IMPLANTS USING CHEMICALLY AMPLIFIED DUV TYPE PHOTORESIST
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Issue Dt:
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05/27/2003
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10126330
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Filing Dt:
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04/19/2002
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Title:
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PROGRAMMING WITH FLOATING SOURCE FOR LOW POWER, LOW LEAKAGE AND HIGH DENSITY FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/10/2003
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10126363
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Filing Dt:
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04/19/2002
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Title:
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NOVEL METHOD TO DISTINGUISH AN STI OUTER EDGE CURRENT COMPONENT WITH AN STI NORMAL CURRENT COMPONENT
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10126814
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Filing Dt:
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04/19/2002
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Title:
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METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
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Issue Dt:
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07/20/2004
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10126840
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Filing Dt:
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04/19/2002
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Title:
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METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON TUNNEL OXIDES USING PARTIAL NITRIDE STRIP AND SMALL BIRD'S BEAK FORMATION FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
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Issue Dt:
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02/10/2004
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Application #:
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10126841
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Filing Dt:
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04/19/2002
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Title:
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REPLACING A FIRST LINER LAYER WITH A THICKER OXIDE LAYER WHEN FORMING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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10128771
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Filing Dt:
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04/22/2002
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Title:
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SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
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Patent #:
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Issue Dt:
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09/16/2003
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10136033
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Filing Dt:
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04/29/2002
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Title:
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SYSTEM FOR PROGRAMMING A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10136034
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Filing Dt:
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04/29/2002
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Pub Dt:
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10/30/2003
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Title:
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SYSTEM FOR CONTROL OF PRE-CHARGE LEVELS IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/28/2004
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10136173
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Filing Dt:
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05/01/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
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Issue Dt:
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02/15/2005
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Application #:
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10139745
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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MEMORY DEVICE WITH A SELF-ASSEMBLED POLYMER FILM AND METHOD OF MAKING THE SAME
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Issue Dt:
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07/15/2003
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10143449
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Filing Dt:
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05/10/2002
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Title:
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SYSTEM FOR READING A DOUBLE-BIT MEMORY CELL
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Issue Dt:
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02/17/2004
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10145952
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Filing Dt:
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05/15/2002
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Title:
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REPLACING LAYERS OF AN INTERGATE DIELECTRIC LAYER WITH HIGH-K MATERIAL FOR IMPROVED SCALABILITY
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01/24/2006
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10146074
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05/16/2002
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Pub Dt:
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03/27/2003
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Title:
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METHOD FOR ERROR DETECTION/CORRECTION OF MULTILEVEL CELL MEMORY AND MULTILEVEL CELL MEMORY HAVING ERROR DETECTION/CORRECTION FUNCTION
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Issue Dt:
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04/15/2003
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10147622
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Filing Dt:
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05/16/2002
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Title:
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NON-VOLATILE MEMORY DIELECTRIC AS CHARGE PUMP DIELECTRIC
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08/26/2003
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10150204
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Filing Dt:
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05/15/2002
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Title:
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SELF-ALIGNED POLYSILICON POLISH
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Issue Dt:
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10/26/2004
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10150240
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Filing Dt:
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05/15/2002
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Title:
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METHOD AND SYSTEM FOR TAILORING CORE AND PERIPHERY CELLS IN A NONVOLATILE MEMORY
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Issue Dt:
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10/19/2004
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10150255
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Filing Dt:
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05/15/2002
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Title:
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METHOD AND SYSTEM FOR SCALING NONVOLATILE MEMORY CELLS
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Issue Dt:
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08/12/2003
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10150282
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Filing Dt:
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05/15/2002
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Title:
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METHOD FOR MINIMIZING NITRIDE RESIDUE ON A SILICON WAFER
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Issue Dt:
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11/05/2002
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10150556
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Filing Dt:
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05/17/2002
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Title:
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METHOD FOR FABRICATING SELF-ALIGNED GATE OF FLASH MEMORY CELL
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Issue Dt:
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11/25/2003
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10151576
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Filing Dt:
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05/16/2002
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Title:
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MEMORY MANUFACTURING PROCESS USING BITLINE RAPID THERMAL ANNEAL
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Issue Dt:
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04/24/2007
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10151595
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05/16/2002
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SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH
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07/22/2003
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10152747
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05/21/2002
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Title:
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METHOD OF FORMING LOW RESISTANCE COMMON SOURCE LINE FOR FLASH MEMORY DEVICES
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08/05/2003
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10155500
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05/23/2002
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Title:
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METHOD AND SYSTEM FOR PROVIDING A POLYSILICON STRINGER MONITOR
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01/20/2004
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10158044
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05/30/2002
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Title:
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NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN FABRICATION OF SONOS FLASH MEMORY
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05/11/2004
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10159078
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05/31/2002
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Title:
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SEMICONDUCTOR ISOLATION MATERIAL DEPOSITION SYSTEM AND METHOD
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11/04/2003
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10159323
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05/31/2002
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Title:
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METHOD FOR INCREASING CORE GAIN IN FLASH MEMORY DEVICE USING STRAINED SILICON
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05/11/2004
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10160050
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06/04/2002
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Pub Dt:
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10/17/2002
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Title:
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METHOD OF DRIVING A SEMICONDUCTOR MEMORY
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05/11/2004
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10164895
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06/07/2002
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HIGH DENSITY DUAL BIT FLASH MEMORY CELL WITH NON PLANAR STRUCTURE
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11/02/2004
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10165383
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06/06/2002
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Title:
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METHOD AND SYSTEM FOR DETERMINING FLOW RATES FOR CONTACT FORMATION
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08/19/2003
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10165837
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Filing Dt:
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06/06/2002
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Title:
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HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL
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07/08/2003
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10173262
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Filing Dt:
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06/17/2002
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Title:
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
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Issue Dt:
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12/30/2003
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10174550
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06/18/2002
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Title:
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SHALLOW TRENCH ISOLATION FILL PROCESS
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08/17/2004
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10174734
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Filing Dt:
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06/18/2002
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Title:
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TEST STRUCTURE TO MEASURE INTERLAYER DIELECTRIC EFFECTS AND BREAKDOWN AND DETECT METAL DEFECTS IN FLASH MEMORIES
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Issue Dt:
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09/09/2003
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10176594
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06/21/2002
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Title:
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USE OF HIGH-K DIELECTRIC MATERIAL FOR ONO AND TUNNEL OXIDE TO IMPROVE FLOATING GATE FLASH MEMORY COUPLING
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06/24/2003
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10178106
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Filing Dt:
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06/24/2002
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Title:
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INNOVATIVE NARROW GATE FORMATION FOR FLOATING GATE FLASH TECHNOLOGY
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Issue Dt:
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11/11/2003
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10178144
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Filing Dt:
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06/24/2002
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Title:
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EXTRACTION OF DRAIN JUNCTION OVERLAP WITH THE GATE AND THE CHANNEL LENGTH FOR ULTRA-SMALL CMOS DEVICES WITH ULTRA-THIN GATE OXIDES
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04/15/2003
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10179061
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Filing Dt:
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06/24/2002
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Title:
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NOVEL CAPPING LAYER
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Issue Dt:
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08/31/2004
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10179723
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Filing Dt:
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06/25/2002
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Title:
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PROCESS TO IMPROVE THE VSS LINE FORMATION FOR HIGH DENSITY FLASH MEMORY AND RELATED STRUCTURE ASSOCIATED THEREWITH
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05/27/2003
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10180673
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06/26/2002
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Title:
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2BIT/CELL ARCHITECTURE FOR FLOATING GATE FLASH MEMORY PRODUCT AND ASSOCIATED METHOD
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07/08/2003
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10180772
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06/25/2002
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Title:
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CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
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09/30/2003
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10189651
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07/03/2002
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Title:
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MEMORY DEVICE AND METHOD OF MAKING
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05/30/2006
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10190002
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07/03/2002
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METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY ISOLATION MATERIAL GROWTH
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08/03/2004
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10190397
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07/02/2002
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METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY CMP STOP LAYER FORMATION
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02/22/2005
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10190420
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07/03/2002
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TEST STRUCTURE FOR MEASURING EFFECT OF TRENCH ISOLATION ON OXIDE IN A MEMORY DEVICE
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11/02/2004
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10197116
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07/16/2002
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01/22/2004
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SYSTEM FOR USING A DYNAMIC REFERENCE IN A DOUBLE-BIT CELL MEMORY
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06/15/2004
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10199793
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07/19/2002
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Title:
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NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER
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12/16/2003
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10200330
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07/22/2002
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Title:
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ON-CHIP ERASE PULSE COUNTER FOR EFFICIENT ERASE VERIFY BIST (BUILT-IN-SELF-TEST) MODE
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03/07/2006
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10200518
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07/22/2002
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ADDRESS SEQUENCER WITHIN BIST (BUILT-IN-SELF-TEST) SYSTEM
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04/11/2006
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10200526
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07/22/2002
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Title:
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DIAGNOSTIC MODE FOR TESTING FUNCTIONALITY OF BIST (BUILT-IN-SELF-TEST) BACK-END STATE MACHINE
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10200539
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Filing Dt:
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07/22/2002
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Title:
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GENERATION OF MARGINING VOLTAGE ON-CHIP DURING TESTING CAM PORTION OF FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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10200544
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Filing Dt:
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07/22/2002
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Title:
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ON-CHIP REPAIR OF DEFECTIVE ADDRESS OF CORE FLASH MEMORY CELLS
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10207056
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Filing Dt:
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07/30/2002
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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SEMICONDUCTOR MEMORY AND METHOD OF DRIVING THE SAME
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10210378
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Filing Dt:
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07/31/2002
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Title:
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SYSTEM AND METHOD FOR ERASE VOLTAGE CONTROL DURING MULTIPLE SECTOR ERASE OF A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10211317
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Filing Dt:
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08/05/2002
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Title:
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NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
|
11/04/2003
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Application #:
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10215140
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Filing Dt:
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08/07/2002
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Title:
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METHOD FOR REPAIRING OVER-ERASURE OF FAST BITS IN FLOATING GATE MEMORY DEVICES
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Patent #:
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Issue Dt:
|
10/26/2004
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Application #:
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10217403
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Filing Dt:
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08/14/2002
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Title:
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REFLOWABLE-DOPED HDP FILM
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10217807
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Filing Dt:
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08/12/2002
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Title:
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METHOD OF PROTECTING A STACKED GATE STRUCTURE DURING FABRICATION
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10217821
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Filing Dt:
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08/12/2002
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Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10217965
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Filing Dt:
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08/12/2002
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Title:
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METHOD AND SYSTEM FOR DETECTING TUNNEL OXIDE ENCROACHMENT ON A MEMORY DEVICE
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Patent #:
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Issue Dt:
|
11/01/2005
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Application #:
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10221682
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Filing Dt:
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09/13/2002
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Publication #:
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Pub Dt:
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03/13/2003
| | | | |
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Title:
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OPTICAL DISK HAVING SYNCHRONIZATION REGION FORMED BETWEEN PRE-RECORDED AREA AND RECORDABLE AREA
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10223195
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
|
04/15/2003
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Application #:
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10223486
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Filing Dt:
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08/19/2002
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Title:
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SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
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Patent #:
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Issue Dt:
|
06/22/2004
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Application #:
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10223920
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Filing Dt:
|
08/20/2002
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Title:
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MEMORY DEVICE AND METHOD OF MAKING
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Patent #:
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Issue Dt:
|
11/16/2004
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Application #:
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10224028
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Filing Dt:
|
08/19/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED
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Patent #:
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|
Issue Dt:
|
07/06/2004
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Application #:
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10224737
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Filing Dt:
|
08/20/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
|
04/26/2005
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Application #:
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10225052
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Filing Dt:
|
08/20/2002
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Title:
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METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
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Patent #:
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Issue Dt:
|
08/03/2004
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Application #:
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10226912
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Filing Dt:
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08/22/2002
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Publication #:
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Pub Dt:
|
02/26/2004
| | | | |
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Title:
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PRECHARGING SCHEME FOR READING A MEMORY CELL
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Patent #:
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Issue Dt:
|
03/16/2004
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Application #:
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10230729
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Filing Dt:
|
08/29/2002
|
|
Title:
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DUMMY WORDLINE FOR ERASE AND BITLINE LEAKAGE
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Patent #:
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Issue Dt:
|
12/07/2004
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Application #:
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10232487
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Filing Dt:
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08/30/2002
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Title:
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FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
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Patent #:
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Issue Dt:
|
06/01/2004
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Application #:
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10233906
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Filing Dt:
|
09/03/2002
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Title:
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FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
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|
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Patent #:
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Issue Dt:
|
07/20/2004
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Application #:
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10237805
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Filing Dt:
|
09/10/2002
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|
Publication #:
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Pub Dt:
|
01/09/2003
| | | | |
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Title:
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METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
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|
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Patent #:
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Issue Dt:
|
04/06/2004
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Application #:
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10238412
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Filing Dt:
|
09/10/2002
|
|
Title:
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VIRTUAL GROUND SILICIDE BIT LINE PROCESS FOR FLOATING GATE FLASH MEMORY
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|
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Patent #:
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|
Issue Dt:
|
11/09/2004
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Application #:
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10238880
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Filing Dt:
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09/11/2002
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Publication #:
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Pub Dt:
|
03/20/2003
| | | | |
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Title:
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MEMORY DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
08/10/2004
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Application #:
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10243108
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Filing Dt:
|
09/13/2002
|
|
Title:
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MEMORY WORDLINE SPACER
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|
|
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Patent #:
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|
Issue Dt:
|
11/28/2006
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Application #:
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10243315
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Filing Dt:
|
09/12/2002
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Publication #:
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Pub Dt:
|
03/18/2004
| | | | |
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Title:
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SYSTEM AND METHOD FOR Y-DECODING IN A FLASH MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
|
04/27/2004
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Application #:
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10243433
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Filing Dt:
|
09/12/2002
|
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Title:
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PATH GATE DRIVER CIRCUIT
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|
|
|
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Patent #:
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|
Issue Dt:
|
06/01/2004
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Application #:
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10243792
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Filing Dt:
|
09/12/2002
|
|
Title:
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METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
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|
|
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Patent #:
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|
Issue Dt:
|
09/30/2003
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Application #:
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10244129
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Filing Dt:
|
09/13/2002
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Title:
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A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-MICRON FLASH MEMORY SEMICONDUCTOR DEVICE
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|
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Patent #:
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|
Issue Dt:
|
12/09/2003
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Application #:
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10244229
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Filing Dt:
|
09/16/2002
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Title:
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HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
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Patent #:
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|
Issue Dt:
|
09/28/2004
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Application #:
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10244369
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Filing Dt:
|
09/16/2002
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Title:
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METHODS FOR FABRICATING AND PLANARIZING DUAL POLY SCALABLE SONOS FLASH MEMORY
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Patent #:
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Issue Dt:
|
06/22/2004
|
Application #:
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10245146
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Filing Dt:
|
09/16/2002
|
|
Title:
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REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
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|
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Patent #:
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|
Issue Dt:
|
05/24/2005
|
Application #:
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10247641
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Filing Dt:
|
09/18/2002
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Title:
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A MULTI-BIT SILICON NITRIDE CHARGE-TRAPPING NON-VOLATILE MEMORY CELL
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