Patent Assignment Details
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| Reel/Frame: | 010689/0160 | |
| Pages: | 4 |
| | Recorded: | 03/16/2000 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09527043
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Filing Dt:
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03/16/2000
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Title:
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Integrated data input sorting and timing circuit for double data rate (ddr) dynamic random access memory ( dram) devices
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Assignee
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| SCIENCE-BASED INDUSTRIAL PARK |
| NO. 1 CREATION ROAD 1 |
| HSINCHU, TAIWAN R.O.C |
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Correspondence name and address
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HOGAN & HARTSON LLP
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WILLIAM J. KUBIDA
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1200 17TH STREET
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SUITE 1500
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DENVER, CO 80202
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