Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 052303/0160 | |
| Pages: | 19 |
| | Recorded: | 04/03/2020 | | |
| Attorney Dkt #: | 5059-500027 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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10/02/2012
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Application #:
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11373928
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Filing Dt:
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03/13/2006
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Publication #:
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Pub Dt:
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09/13/2007
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Title:
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TRANCEIVER NON-LINEARITY CANCELLATION
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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11725528
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Filing Dt:
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03/19/2007
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Publication #:
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Pub Dt:
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09/25/2008
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Title:
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SELECTION OF FILTER COEFFICIENTS FOR TRANCEIVER NON-LINEARITY SIGNAL CANCELLATION
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Patent #:
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Issue Dt:
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04/09/2013
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Application #:
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12077672
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Filing Dt:
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03/20/2008
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Publication #:
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Pub Dt:
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09/24/2009
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Title:
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GENERATING AN ESTIMATED NON-LINEAR ECHO SIGNAL
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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12384298
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Filing Dt:
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04/02/2009
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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INTERFACING MEDIA ACCESS CONTROL (MAC) WITH A LOW-POWER PHYSICAL LAYER (PHY) CONTROL
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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12765097
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Filing Dt:
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04/22/2010
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Publication #:
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Pub Dt:
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10/27/2011
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Title:
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REDUCING TRANSMIT SIGNAL COMPONENTS OF A RECEIVE SIGNAL OF A TRANSCEIVER
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Patent #:
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Issue Dt:
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08/28/2012
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Application #:
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12839254
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Filing Dt:
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07/19/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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REDUCING TRANSMIT SIGNAL COMPONENTS OF A RECEIVE SIGNAL OF A TRANSCEIVER USING A SHARED DAC ARCHITECTURE
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Patent #:
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Issue Dt:
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02/04/2020
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Application #:
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16365516
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Filing Dt:
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03/26/2019
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Title:
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SIMULTANEOUS BIDIRECTIONAL SERIAL LINK INTERFACE WITH OPTIMIZED HYBRID CIRCUIT
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Assignee
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| PO BOX 1350, CLIFTON HOUSE |
| 75 FORT STREET |
| GRAND CAYMAN, CAYMAN ISLANDS KY1-1108 |
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Correspondence name and address
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HARNESS, DICKEY & PIERCE, P.L.C.
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P.O. BOX 828
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BLOOMFIELD HILLS, MI 48303
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