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Reel/Frame:	052561/0161			Pages:	20
		Recorded:	05/04/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 316
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Patent #:	6368953	Issue Dt:	04/09/2002	Application #:	09567466	Filing Dt:	05/09/2000
Title:	ENCAPSULATED METAL STRUCTURES FOR SEMICONDUCTOR DEVICES AND MIM CAPACITORS INCLUDING THE SAME

Patent #:	6504210	Issue Dt:	01/07/2003	Application #:	09599484	Filing Dt:	06/23/2000
Title:	FULLY ENCAPSULATED DAMASCENE GATES FOR GIGABIT DRAMS

Patent #:	6597068	Issue Dt:	07/22/2003	Application #:	10034862	Filing Dt:	12/28/2001
Publication #:	US20020068431	Pub Dt:	06/06/2002
Title:	ENCAPSULATED METAL STRUCTURES FOR SEMICONDUCTOR DEVICES AND MIM CAPACITORS INCLUDING THE SAME

Patent #:	6756624	Issue Dt:	06/29/2004	Application #:	10409010	Filing Dt:	04/07/2003
Publication #:	US20030211698	Pub Dt:	11/13/2003
Title:	ENCAPSULATED METAL STRUCTURES FOR SEMICONDUCTOR DEVICES AND MIM CAPACITORS INCLUDING THE SAME

Patent #:	6825075	Issue Dt:	11/30/2004	Application #:	10757214	Filing Dt:	01/14/2004
Publication #:	US20040147089	Pub Dt:	07/29/2004
Title:	METHOD OF FABRICATING MIM CAPACITOR WITH THE ENCAPSULATED METAL STRUCTURE SERVING AS THE LOWER PLATE

Patent #:	7521307	Issue Dt:	04/21/2009	Application #:	11380695	Filing Dt:	04/28/2006
Publication #:	US20070252214	Pub Dt:	11/01/2007
Title:	CMOS STRUCTURES AND METHODS USING SELF-ALIGNED DUAL STRESSED LAYERS

Patent #:	8901662	Issue Dt:	12/02/2014	Application #:	11757792	Filing Dt:	06/04/2007
Publication #:	US20070252230	Pub Dt:	11/01/2007
Title:	CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD

Patent #:	7820555	Issue Dt:	10/26/2010	Application #:	11870577	Filing Dt:	10/11/2007
Publication #:	US20090098737	Pub Dt:	04/16/2009
Title:	METHOD OF PATTERNING MULTILAYER METAL GATE STRUCTURES FOR CMOS DEVICES

Patent #:	7898021	Issue Dt:	03/01/2011	Application #:	11924699	Filing Dt:	10/26/2007
Publication #:	US20090108324	Pub Dt:	04/30/2009
Title:	SEMICONDUCTOR FIN BASED NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATION THEREOF

Patent #:	8227307	Issue Dt:	07/24/2012	Application #:	12490353	Filing Dt:	06/24/2009
Publication #:	US20100330810	Pub Dt:	12/30/2010
Title:	METHOD FOR REMOVING THRESHOLD VOLTAGE ADJUSTING LAYER WITH EXTERNAL ACID DIFFUSION PROCESS

Patent #:	8105887	Issue Dt:	01/31/2012	Application #:	12500107	Filing Dt:	07/09/2009
Publication #:	US20110006371	Pub Dt:	01/13/2011
Title:	INDUCING STRESS IN CMOS DEVICE

Patent #:	8686508	Issue Dt:	04/01/2014	Application #:	12553523	Filing Dt:	09/03/2009
Publication #:	US20110049683	Pub Dt:	03/03/2011
Title:	STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES

Patent #:	8232627	Issue Dt:	07/31/2012	Application #:	12563195	Filing Dt:	09/21/2009
Publication #:	US20110068399	Pub Dt:	03/24/2011
Title:	INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE

Patent #:	8232179	Issue Dt:	07/31/2012	Application #:	12571483	Filing Dt:	10/01/2009
Publication #:	US20110081765	Pub Dt:	04/07/2011
Title:	METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION

Patent #:	8287980	Issue Dt:	10/16/2012	Application #:	12608363	Filing Dt:	10/29/2009
Publication #:	US20110104426	Pub Dt:	05/05/2011
Title:	EDGE PROTECTION SEAL FOR BONDED SUBSTRATES

Patent #:	8415238	Issue Dt:	04/09/2013	Application #:	12687282	Filing Dt:	01/14/2010
Publication #:	US20110171827	Pub Dt:	07/14/2011
Title:	THREE DIMENSIONAL INTEGRATION AND METHODS OF THROUGH SILICON VIA CREATION

Patent #:	8338286	Issue Dt:	12/25/2012	Application #:	12897826	Filing Dt:	10/05/2010
Publication #:	US20120083114	Pub Dt:	04/05/2012
Title:	DIMENSIONALLY DECOUPLED BALL LIMITING METALURGY

Patent #:	8753460	Issue Dt:	06/17/2014	Application #:	13015638	Filing Dt:	01/28/2011
Publication #:	US20120193014	Pub Dt:	08/02/2012
Title:	REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

Patent #:	8652914	Issue Dt:	02/18/2014	Application #:	13039678	Filing Dt:	03/03/2011
Publication #:	US20120223372	Pub Dt:	09/06/2012
Title:	TWO-STEP SILICIDE FORMATION

Patent #:	8541814	Issue Dt:	09/24/2013	Application #:	13084594	Filing Dt:	04/12/2011
Publication #:	US20120261672	Pub Dt:	10/18/2012
Title:	MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS

Patent #:	8435891	Issue Dt:	05/07/2013	Application #:	13151646	Filing Dt:	06/02/2011
Publication #:	US20120306093	Pub Dt:	12/06/2012
Title:	CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE

Patent #:	8492897	Issue Dt:	07/23/2013	Application #:	13232085	Filing Dt:	09/14/2011
Publication #:	US20130062769	Pub Dt:	03/14/2013
Title:	MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES

Patent #:	8169026	Issue Dt:	05/01/2012	Application #:	13242380	Filing Dt:	09/23/2011
Publication #:	US20120007190	Pub Dt:	01/12/2012
Title:	STRESS-INDUCED CMOS DEVICE

Patent #:	8659156	Issue Dt:	02/25/2014	Application #:	13275352	Filing Dt:	10/18/2011
Publication #:	US20130093089	Pub Dt:	04/18/2013
Title:	INTERCONNECT STRUCTURE WITH AN ELECTROMIGRATION AND STRESS MIGRATION ENHANCEMENT LINER

Patent #:	8916950	Issue Dt:	12/23/2014	Application #:	13275729	Filing Dt:	10/18/2011
Publication #:	US20130093040	Pub Dt:	04/18/2013
Title:	SHALLOW TRENCH ISOLATION STRUCTURE HAVING A NITRIDE PLUG

Patent #:	8936293	Issue Dt:	01/20/2015	Application #:	13333688	Filing Dt:	12/21/2011
Publication #:	US20130164113	Pub Dt:	06/27/2013
Title:	ROBOTIC DEVICE FOR SUBSTRATE TRANSFER APPLICATIONS

Patent #:	8878071	Issue Dt:	11/04/2014	Application #:	13352151	Filing Dt:	01/17/2012
Publication #:	US20120186793	Pub Dt:	07/26/2012
Title:	INTEGRATED DEVICE WITH DEFINED HEAT FLOW

Patent #:	8962423	Issue Dt:	02/24/2015	Application #:	13352655	Filing Dt:	01/18/2012
Publication #:	US20130181326	Pub Dt:	07/18/2013
Title:	MULTILAYER MIM CAPACITOR

Patent #:	8643191	Issue Dt:	02/04/2014	Application #:	13358792	Filing Dt:	01/26/2012
Publication #:	US20130193584	Pub Dt:	08/01/2013
Title:	ON-CHIP RADIAL CAVITY POWER DIVIDER/COMBINER

Patent #:	8946027	Issue Dt:	02/03/2015	Application #:	13367725	Filing Dt:	02/07/2012
Publication #:	US20130200454	Pub Dt:	08/08/2013
Title:	REPLACEMENT-GATE FINFET STRUCTURE AND PROCESS

Patent #:	8679941	Issue Dt:	03/25/2014	Application #:	13422138	Filing Dt:	03/16/2012
Publication #:	US20120178236	Pub Dt:	07/12/2012
Title:	METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION

Patent #:	8569154	Issue Dt:	10/29/2013	Application #:	13422415	Filing Dt:	03/16/2012
Publication #:	US20120190189	Pub Dt:	07/26/2012
Title:	THREE DIMENSIONAL INTEGRATION AND METHODS OF THROUGH SILICON VIA CREATION

Patent #:	8492252	Issue Dt:	07/23/2013	Application #:	13422445	Filing Dt:	03/16/2012
Publication #:	US20120190196	Pub Dt:	07/26/2012
Title:	THREE DIMENSIONAL INTEGRATION AND METHODS OF THROUGH SILICON VIA CREATION

Patent #:	9245788	Issue Dt:	01/26/2016	Application #:	13443963	Filing Dt:	04/11/2012
Publication #:	US20130270709	Pub Dt:	10/17/2013
Title:	NON-BRIDGING CONTACT VIA STRUCTURES IN PROXIMITY

Patent #:	8507333	Issue Dt:	08/13/2013	Application #:	13455176	Filing Dt:	04/25/2012
Publication #:	US20120208329	Pub Dt:	08/16/2012
Title:	INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE

Patent #:	8791005	Issue Dt:	07/29/2014	Application #:	13525823	Filing Dt:	06/18/2012
Publication #:	US20130334691	Pub Dt:	12/19/2013
Title:	SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS

Patent #:	9024387	Issue Dt:	05/05/2015	Application #:	13532311	Filing Dt:	06/25/2012
Publication #:	US20130341724	Pub Dt:	12/26/2013
Title:	FinFET with Body Contact

Patent #:	8679611	Issue Dt:	03/25/2014	Application #:	13556369	Filing Dt:	07/24/2012
Publication #:	US20120288687	Pub Dt:	11/15/2012
Title:	EDGE PROTECTION SEAL FOR BONDED SUBSTRATES

Patent #:	8969213	Issue Dt:	03/03/2015	Application #:	13561122	Filing Dt:	07/30/2012
Publication #:	US20140027917	Pub Dt:	01/30/2014
Title:	NON-LITHOGRAPHIC LINE PATTERN FORMATION

Patent #:	9054156	Issue Dt:	06/09/2015	Application #:	13561133	Filing Dt:	07/30/2012
Publication #:	US20140027923	Pub Dt:	01/30/2014
Title:	NON-LITHOGRAPHIC HOLE PATTERN FORMATION

Patent #:	9219059	Issue Dt:	12/22/2015	Application #:	13627162	Filing Dt:	09/26/2012
Publication #:	US20140084412	Pub Dt:	03/27/2014
Title:	SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

Patent #:	8895436	Issue Dt:	11/25/2014	Application #:	13705652	Filing Dt:	12/05/2012
Publication #:	US20140151896	Pub Dt:	06/05/2014
Title:	IMPLEMENTING ENHANCED POWER SUPPLY DISTRIBUTION AND DECOUPLING UTILIZING TSV EXCLUSION ZONE

Patent #:	9082624	Issue Dt:	07/14/2015	Application #:	13732525	Filing Dt:	01/02/2013
Publication #:	US20140184320	Pub Dt:	07/03/2014
Title:	SIGNAL PATH OF A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE

Patent #:	8629510	Issue Dt:	01/14/2014	Application #:	13767088	Filing Dt:	02/14/2013
Publication #:	US20130153974	Pub Dt:	06/20/2013
Title:	TWO-STEP SILICIDE FORMATION

Patent #:	8807184	Issue Dt:	08/19/2014	Application #:	13774136	Filing Dt:	02/22/2013
Publication #:	US20130164912	Pub Dt:	06/27/2013
Title:	REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

Patent #:	8771533	Issue Dt:	07/08/2014	Application #:	13780854	Filing Dt:	02/28/2013
Publication #:	US20130168017	Pub Dt:	07/04/2013
Title:	EDGE PROTECTION SEAL FOR BONDED SUBSTRATES

Patent #:	9021407	Issue Dt:	04/28/2015	Application #:	13787948	Filing Dt:	03/07/2013
Publication #:	US20140184321	Pub Dt:	07/03/2014
Title:	SIGNAL PATH OF A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE

Patent #:	9159558	Issue Dt:	10/13/2015	Application #:	13840880	Filing Dt:	03/15/2013
Publication #:	US20140273476	Pub Dt:	09/18/2014
Title:	METHODS OF REDUCING DEFECTS IN DIRECTED SELF-ASSEMBLED STRUCTURES

Patent #:	9040363	Issue Dt:	05/26/2015	Application #:	13847724	Filing Dt:	03/20/2013
Publication #:	US20140284667	Pub Dt:	09/25/2014
Title:	FINFET WITH REDUCED CAPACITANCE

Patent #:	9601367	Issue Dt:	03/21/2017	Application #:	13849796	Filing Dt:	03/25/2013
Publication #:	US20140284813	Pub Dt:	09/25/2014
Title:	INTERCONNECT LEVEL STRUCTURES FOR CONFINING STITCH-INDUCED VIA STRUCTURES

Patent #:	9006071	Issue Dt:	04/14/2015	Application #:	13851204	Filing Dt:	03/27/2013
Publication #:	US20140291734	Pub Dt:	10/02/2014
Title:	THIN CHANNEL MOSFET WITH SILICIDE LOCAL INTERCONNECT

Patent #:	8853085	Issue Dt:	10/07/2014	Application #:	13868564	Filing Dt:	04/23/2013
Publication #:	US20140315390	Pub Dt:	10/23/2014
Title:	GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN

Patent #:	8586431	Issue Dt:	11/19/2013	Application #:	13871026	Filing Dt:	04/26/2013
Publication #:	US20130237054	Pub Dt:	09/12/2013
Title:	THREE DIMENSIONAL INTEGRATION AND METHODS OF THROUGH SILICON VIA CREATION

Patent #:	8927427	Issue Dt:	01/06/2015	Application #:	13872371	Filing Dt:	04/29/2013
Publication #:	US20140319694	Pub Dt:	10/30/2014
Title:	ANTICIPATORY IMPLANT FOR TSV

Patent #:	8993395	Issue Dt:	03/31/2015	Application #:	13923704	Filing Dt:	06/21/2013
Publication #:	US20130288440	Pub Dt:	10/31/2013
Title:	MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS

Patent #:	8647954	Issue Dt:	02/11/2014	Application #:	13937698	Filing Dt:	07/09/2013
Publication #:	US20130295765	Pub Dt:	11/07/2013
Title:	TWO-STEP SILICIDE FORMATION

Patent #:	9029949	Issue Dt:	05/12/2015	Application #:	14036158	Filing Dt:	09/25/2013
Publication #:	US20150084128	Pub Dt:	03/26/2015
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES WITH LOCAL HEAT DISSIPATER(S) AND METHODS

Patent #:	9543175	Issue Dt:	01/10/2017	Application #:	14036999	Filing Dt:	09/25/2013
Publication #:	US20150083638	Pub Dt:	03/26/2015
Title:	PACKAGE ASSEMBLY FOR THIN WAFER SHIPPING AND METHOD OF USE

Patent #:	9018754	Issue Dt:	04/28/2015	Application #:	14041716	Filing Dt:	09/30/2013
Publication #:	US20150091129	Pub Dt:	04/02/2015
Title:	HEAT DISSIPATIVE ELECTRICAL ISOLATION/INSULATION STRUCTURE FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING

Patent #:	9040407	Issue Dt:	05/26/2015	Application #:	14043079	Filing Dt:	10/01/2013
Publication #:	US20140027296	Pub Dt:	01/30/2014
Title:	SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS

Patent #:	9060457	Issue Dt:	06/16/2015	Application #:	14043104	Filing Dt:	10/01/2013
Publication #:	US20140027911	Pub Dt:	01/30/2014
Title:	SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS

Patent #:	9055703	Issue Dt:	06/09/2015	Application #:	14043127	Filing Dt:	10/01/2013
Publication #:	US20140027912	Pub Dt:	01/30/2014
Title:	SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS

Patent #:	8828870	Issue Dt:	09/09/2014	Application #:	14152127	Filing Dt:	01/10/2014
Publication #:	US20140127899	Pub Dt:	05/08/2014
Title:	MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES

Patent #:	9881810	Issue Dt:	01/30/2018	Application #:	14154273	Filing Dt:	01/14/2014
Publication #:	US20140124903	Pub Dt:	05/08/2014
Title:	STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES

Patent #:	8802559	Issue Dt:	08/12/2014	Application #:	14181079	Filing Dt:	02/14/2014
Publication #:	US20140162450	Pub Dt:	06/12/2014
Title:	INTERCONNECT STRUCTURE WITH AN ELECTROMIGRATION AND STRESS MIGRATION ENHANCEMENT LINER

Patent #:	9685362	Issue Dt:	06/20/2017	Application #:	14183631	Filing Dt:	02/19/2014
Publication #:	US20150235881	Pub Dt:	08/20/2015
Title:	APPARATUS AND METHOD FOR CENTERING SUBSTRATES ON A CHUCK

Patent #:	9431339	Issue Dt:	08/30/2016	Application #:	14184003	Filing Dt:	02/19/2014
Publication #:	US20150235945	Pub Dt:	08/20/2015
Title:	WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION

Patent #:	9431250	Issue Dt:	08/30/2016	Application #:	14199282	Filing Dt:	03/06/2014
Publication #:	US20150255286	Pub Dt:	09/10/2015
Title:	DEEP WELL IMPLANT USING BLOCKING MASK

Patent #:	9214332	Issue Dt:	12/15/2015	Application #:	14220288	Filing Dt:	03/20/2014
Publication #:	US20150270124	Pub Dt:	09/24/2015
Title:	COMPOSITE DIELECTRIC MATERIALS WITH IMPROVED MECHANICAL AND ELECTRICAL PROPERTIES

Patent #:	9209017	Issue Dt:	12/08/2015	Application #:	14225810	Filing Dt:	03/26/2014
Publication #:	US20150279667	Pub Dt:	10/01/2015
Title:	ADVANCED ULTRA LOW K SICOH DIELECTRICS PREPARED BY BUILT-IN ENGINEERED PORE SIZE AND BONDING STRUCTURED WITH CYCLIC ORGANOSILICON PRECURSORS

Patent #:	9373524	Issue Dt:	06/21/2016	Application #:	14259657	Filing Dt:	04/23/2014
Publication #:	US20150311088	Pub Dt:	10/29/2015
Title:	DIE LEVEL CHEMICAL MECHANICAL POLISHING

Patent #:	9293375	Issue Dt:	03/22/2016	Application #:	14260724	Filing Dt:	04/24/2014
Publication #:	US20150311121	Pub Dt:	10/29/2015
Title:	SELECTIVELY GROWN SELF-ALIGNED FINS FOR DEEP ISOLATION INTEGRATION

Patent #:	9472415	Issue Dt:	10/18/2016	Application #:	14265402	Filing Dt:	04/30/2014
Publication #:	US20150318184	Pub Dt:	11/05/2015
Title:	DIRECTIONAL CHEMICAL OXIDE ETCH TECHNIQUE

Patent #:	9922851	Issue Dt:	03/20/2018	Application #:	14269457	Filing Dt:	05/05/2014
Publication #:	US20150318260	Pub Dt:	11/05/2015
Title:	GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING

Patent #:	9190285	Issue Dt:	11/17/2015	Application #:	14270565	Filing Dt:	05/06/2014
Publication #:	US20150325450	Pub Dt:	11/12/2015
Title:	REWORK AND STRIPPING OF COMPLEX PATTERNING LAYERS USING CHEMICAL MECHANICAL POLISHING

Patent #:	9312185	Issue Dt:	04/12/2016	Application #:	14270791	Filing Dt:	05/06/2014
Publication #:	US20150325483	Pub Dt:	11/12/2015
Title:	FORMATION OF METAL RESISTOR AND E-FUSE

Patent #:	9275866	Issue Dt:	03/01/2016	Application #:	14277857	Filing Dt:	05/15/2014
Publication #:	US20150332927	Pub Dt:	11/19/2015
Title:	GAS CLUSTER REACTOR FOR ANISOTROPIC FILM GROWTH

Patent #:	9312140	Issue Dt:	04/12/2016	Application #:	14281166	Filing Dt:	05/19/2014
Publication #:	US20150332925	Pub Dt:	11/19/2015
Title:	SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

Patent #:	9443770	Issue Dt:	09/13/2016	Application #:	14282491	Filing Dt:	05/20/2014
Publication #:	US20150340292	Pub Dt:	11/26/2015
Title:	PATTERNING PROCESS FOR FIN IMPLANTATION

Patent #:	9466614	Issue Dt:	10/11/2016	Application #:	14289679	Filing Dt:	05/29/2014
Publication #:	US20150348977	Pub Dt:	12/03/2015
Title:	VERTICALLY INTEGRATED MEMORY CELL

Patent #:	9337088	Issue Dt:	05/10/2016	Application #:	14302757	Filing Dt:	06/12/2014
Publication #:	US20150364398	Pub Dt:	12/17/2015
Title:	MOL RESISTOR WITH METAL GRID HEAT SHIELD

Patent #:	9589827	Issue Dt:	03/07/2017	Application #:	14305502	Filing Dt:	06/16/2014
Publication #:	US20150364361	Pub Dt:	12/17/2015
Title:	SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES

Patent #:	9530665	Issue Dt:	12/27/2016	Application #:	14313340	Filing Dt:	06/24/2014
Publication #:	US20150371867	Pub Dt:	12/24/2015
Title:	PROTECTIVE TRENCH LAYER AND GATE SPACER IN FINFET DEVICES

Patent #:	9123658	Issue Dt:	09/01/2015	Application #:	14327968	Filing Dt:	07/10/2014
Publication #:	US20140322917	Pub Dt:	10/30/2014
Title:	GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN

Patent #:	9396957	Issue Dt:	07/19/2016	Application #:	14456212	Filing Dt:	08/11/2014
Publication #:	US20140349088	Pub Dt:	11/27/2014
Title:	NON-LITHOGRAPHIC LINE PATTERN FORMATION

Patent #:	9330962	Issue Dt:	05/03/2016	Application #:	14457176	Filing Dt:	08/12/2014
Publication #:	US20140346640	Pub Dt:	11/27/2014
Title:	NON-LITHOGRAPHIC HOLE PATTERN FORMATION

Patent #:	9318347	Issue Dt:	04/19/2016	Application #:	14459745	Filing Dt:	08/14/2014
Publication #:	US20160049311	Pub Dt:	02/18/2016
Title:	WAFER BACKSIDE PARTICLE MITIGATION

Patent #:	9240447	Issue Dt:	01/19/2016	Application #:	14465365	Filing Dt:	08/21/2014
Title:	FINFETs CONTAINING IMPROVED STRAIN BENEFIT AND SELF ALIGNED TRENCH ISOLATION STRUCTURES

Patent #:	9478453	Issue Dt:	10/25/2016	Application #:	14488496	Filing Dt:	09/17/2014
Publication #:	US20160079117	Pub Dt:	03/17/2016
Title:	Sacrificial Carrier Dicing of Semiconductor Wafers

Patent #:	9406554	Issue Dt:	08/02/2016	Application #:	14501137	Filing Dt:	09/30/2014
Publication #:	US20160093526	Pub Dt:	03/31/2016
Title:	DIFFUSION BARRIER LAYER FORMATION

Patent #:	9406563	Issue Dt:	08/02/2016	Application #:	14501445	Filing Dt:	09/30/2014
Publication #:	US20150104922	Pub Dt:	04/16/2015
Title:	INTEGRATED DEVICE WITH DEFINED HEAT FLOW

Patent #:	9502418	Issue Dt:	11/22/2016	Application #:	14504964	Filing Dt:	10/02/2014
Publication #:	US20160099245	Pub Dt:	04/07/2016
Title:	SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Patent #:	9443929	Issue Dt:	09/13/2016	Application #:	14532230	Filing Dt:	11/04/2014
Publication #:	US20150054080	Pub Dt:	02/26/2015
Title:	SHALLOW TRENCH ISOLATION STRUCTURE HAVING A NITRIDE PLUG

Patent #:	9224801	Issue Dt:	12/29/2015	Application #:	14532281	Filing Dt:	11/04/2014
Publication #:	US20150054130	Pub Dt:	02/26/2015
Title:	MULTILAYER MIM CAPACITOR

Patent #:	9691900	Issue Dt:	06/27/2017	Application #:	14551260	Filing Dt:	11/24/2014
Publication #:	US20160148933	Pub Dt:	05/26/2016
Title:	DUAL EPITAXY CMOS PROCESSING USING SELECTIVE NITRIDE FORMATION FOR REDUCED GATE PITCH

Patent #:	9318344	Issue Dt:	04/19/2016	Application #:	14556732	Filing Dt:	12/01/2014
Publication #:	US20150087121	Pub Dt:	03/26/2015
Title:	CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD

Patent #:	9406683	Issue Dt:	08/02/2016	Application #:	14560203	Filing Dt:	12/04/2014
Publication #:	US20160163711	Pub Dt:	06/09/2016
Title:	WET BOTTLING PROCESS FOR SMALL DIAMETER DEEP TRENCH CAPACITORS

Patent #:	9245884	Issue Dt:	01/26/2016	Application #:	14568531	Filing Dt:	12/12/2014
Title:	STRUCTURE FOR METAL OXIDE SEMICONDUCTOR CAPACITOR

Patent #:	9660059	Issue Dt:	05/23/2017	Application #:	14568969	Filing Dt:	12/12/2014
Publication #:	US20160172462	Pub Dt:	06/16/2016
Title:	FIN REPLACEMENT IN A FIELD-EFFECT TRANSISTOR

100

Patent #:	9443799	Issue Dt:	09/13/2016	Application #:	14571352	Filing Dt:	12/16/2014
Publication #:	US20160172288	Pub Dt:	06/16/2016
Title:	INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

03/06/2020

Assignee

ELPIS TECHNOLOGIES INC.

1891 ROBERTSON ROAD

SUITE 100

OTTAWA, CANADA K2H 5B7

Correspondence name and address
	ELPIS TECHNOLOGIES INC.
	1891 ROBERTSON ROAD
	SUITE 100
	OTTAWA, K2H 5B7 CANADA

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