Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 025376/0162 | |
| Pages: | 29 |
| | Recorded: | 11/16/2010 | | |
| Attorney Dkt #: | NGR |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
8
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
09648372
|
Filing Dt:
|
08/25/2000
|
|
Title:
|
PATTERN INSPECTION APPARATUS, PATTERN INSPECTION METHOD, AND RECORDING MEDIUM
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10689021
|
Filing Dt:
|
10/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
Pattern inspection apparatus and method
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11044159
|
Filing Dt:
|
01/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
PATTERN INSPECTION APPARATUS, PATTERN INSPECTION METHOD, AND RECORDING MEDIUM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
11058616
|
Filing Dt:
|
02/16/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
PATTERN INSPECTION APPARATUS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11434797
|
Filing Dt:
|
05/17/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
PATTERN INSPECTION APPARATUS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
11987766
|
Filing Dt:
|
12/04/2007
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
|
Title:
|
PATTERN INSPECTION APPARATUS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12637331
|
Filing Dt:
|
12/14/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
|
Title:
|
DEFECT AND CRITICAL DIMENSION ANALYSIS SYSTEMS AND METHODS FOR A SEMICONDUCTOR LITHOGRAPHIC PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12725141
|
Filing Dt:
|
03/16/2010
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR A SEMICONDUCTOR LITHOGRAPHIC PROCESS CONTROL USING STATISTICAL INFORMATION IN DEFECT IDENTIFICATION
|
|
|
Assignee
|
|
|
|
|
| 7F NK SHIMURASAKAUE BLDG. |
| 3-6-7 AZUSAWA, ITABASHI-KU, |
| TOKYO, JAPAN 174-0051 |
|
|
Correspondence name and address
|
| |
LATHROP & GAGE LLP
|
| |
4845 PEARL EAST CIRCLE
|
| |
SUITE 201
|
| |
BOULDER, CO 80301
|
Search Results as of:
05/24/2024 06:38 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
