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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:048559/0162   Pages: 20
Recorded: 03/11/2019
Attorney Dkt #:EASIC
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 47
1
Patent #:
6194912
Issue Dt:
02/27/2001
Application #:
09265998
Filing Dt:
03/11/1999
Title:
INTEGRATED CIRCUIT DEVICE
2
Patent #:
6236229
Issue Dt:
05/22/2001
Application #:
09310962
Filing Dt:
05/13/1999
Title:
SEMICONDUCTOR DEVICE
3
Patent #:
6331733
Issue Dt:
12/18/2001
Application #:
09371031
Filing Dt:
08/10/1999
Title:
SEMICONDUCTOR DEVICE
4
Patent #:
6245634
Issue Dt:
06/12/2001
Application #:
09428460
Filing Dt:
10/28/1999
Title:
METHOD FOR DESIGN AND MANUFACTURE OF SEMICONDUCTORS
5
Patent #:
6331790
Issue Dt:
12/18/2001
Application #:
09659783
Filing Dt:
09/11/2000
Title:
Customizable and programmable cell array
6
Patent #:
6331789
Issue Dt:
12/18/2001
Application #:
09756903
Filing Dt:
01/10/2001
Publication #:
US20010003428
Pub Dt:
06/14/2001
Title:
Semiconductor device
7
Patent #:
6756811
Issue Dt:
06/29/2004
Application #:
09803373
Filing Dt:
03/12/2001
Publication #:
US20010038297
Pub Dt:
11/08/2001
Title:
CUSTOMIZABLE AND PROGRAMMABLE CELL ARRAY
8
Patent #:
6686253
Issue Dt:
02/03/2004
Application #:
09829939
Filing Dt:
04/11/2001
Publication #:
US20010036688
Pub Dt:
11/01/2001
Title:
METHOD FOR DESIGN AND MANUFACTURE OF SEMICONDUCTORS
9
Patent #:
6476493
Issue Dt:
11/05/2002
Application #:
09940714
Filing Dt:
08/29/2001
Publication #:
US20020024143
Pub Dt:
02/28/2002
Title:
SEMICONDUCTOR DEVICE
10
Patent #:
6642744
Issue Dt:
11/04/2003
Application #:
09970871
Filing Dt:
10/05/2001
Publication #:
US20020043988
Pub Dt:
04/18/2002
Title:
CUSTOMIZABLE AND PROGRAMMABLE CELL ARRAY
11
Patent #:
6823499
Issue Dt:
11/23/2004
Application #:
10245140
Filing Dt:
09/16/2002
Title:
METHOD FOR DESIGNING APPLICATION SPECIFIC INTEGRATED CIRCUIT STRUCTURE
12
Patent #:
6953956
Issue Dt:
10/11/2005
Application #:
10321669
Filing Dt:
12/18/2002
Publication #:
US20040119098
Pub Dt:
06/24/2004
Title:
SEMICONDUCTOR DEVICE HAVING BORDERLESS LOGIC ARRAY AND FLEXIBLE I/O
13
Patent #:
6819136
Issue Dt:
11/16/2004
Application #:
10452049
Filing Dt:
06/03/2003
Publication #:
US20030206036
Pub Dt:
11/06/2003
Title:
CUSTOMIZABLE AND PROGRAMMABLE CELL ARRAY
14
Patent #:
7105871
Issue Dt:
09/12/2006
Application #:
10730064
Filing Dt:
12/09/2003
Publication #:
US20040161878
Pub Dt:
08/19/2004
Title:
METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE
15
Patent #:
7098691
Issue Dt:
08/29/2006
Application #:
10899020
Filing Dt:
07/27/2004
Publication #:
US20060022705
Pub Dt:
02/02/2006
Title:
STRUCTURED INTEGRATED CIRCUIT DEVICE
16
Patent #:
6930511
Issue Dt:
08/16/2005
Application #:
10915556
Filing Dt:
08/11/2004
Publication #:
US20050012520
Pub Dt:
01/20/2005
Title:
ARRAY OF PROGRAMMABLE CELLS WITH CUSTOMIZED INTERCONNECTIONS
17
Patent #:
6989687
Issue Dt:
01/24/2006
Application #:
10917396
Filing Dt:
08/13/2004
Publication #:
US20050015699
Pub Dt:
01/20/2005
Title:
CUSTOMIZABLE AND PROGRAMMABLE CELL ARRAY
18
Patent #:
6985012
Issue Dt:
01/10/2006
Application #:
10927470
Filing Dt:
08/27/2004
Publication #:
US20050024086
Pub Dt:
02/03/2005
Title:
CUSTOMIZABLE AND PROGRAMMABLE CELL ARRAY
19
Patent #:
NONE
Issue Dt:
Application #:
11097168
Filing Dt:
04/04/2005
Publication #:
US20050167701
Pub Dt:
08/04/2005
Title:
Method for fabrication of semiconductor device
20
Patent #:
7157937
Issue Dt:
01/02/2007
Application #:
11186923
Filing Dt:
07/22/2005
Publication #:
US20060028241
Pub Dt:
02/09/2006
Title:
STRUCTURED INTEGRATED CIRCUIT DEVICE
21
Patent #:
NONE
Issue Dt:
Application #:
11240380
Filing Dt:
10/03/2005
Publication #:
US20060033124
Pub Dt:
02/16/2006
Title:
Method for fabrication of semiconductor device
22
Patent #:
7068070
Issue Dt:
06/27/2006
Application #:
11244108
Filing Dt:
10/06/2005
Publication #:
US20060028242
Pub Dt:
02/09/2006
Title:
CUSTOMIZABLE AND PROGRAMMABLE CELL ARRAY
23
Patent #:
7439773
Issue Dt:
10/21/2008
Application #:
11246294
Filing Dt:
10/11/2005
Publication #:
US20070080709
Pub Dt:
04/12/2007
Title:
INTEGRATED CIRCUIT COMMUNICATION TECHNIQUES
24
Patent #:
NONE
Issue Dt:
Application #:
11278452
Filing Dt:
04/03/2006
Publication #:
US20060176075
Pub Dt:
08/10/2006
Title:
Customizable and Programmable Cell Array
25
Patent #:
7689960
Issue Dt:
03/30/2010
Application #:
11338804
Filing Dt:
01/25/2006
Publication #:
US20070174801
Pub Dt:
07/26/2007
Title:
PROGRAMMABLE VIA MODELING
26
Patent #:
NONE
Issue Dt:
Application #:
11354957
Filing Dt:
02/16/2006
Publication #:
US20070187808
Pub Dt:
08/16/2007
Title:
Customizable power and ground pins
27
Patent #:
7514959
Issue Dt:
04/07/2009
Application #:
11356076
Filing Dt:
02/17/2006
Publication #:
US20060139057
Pub Dt:
06/29/2006
Title:
STRUCTURED INTEGRATED CIRCUIT DEVICE
28
Patent #:
7550996
Issue Dt:
06/23/2009
Application #:
11366528
Filing Dt:
03/03/2006
Publication #:
US20060164121
Pub Dt:
07/27/2006
Title:
STRUCTURED INTEGRATED CIRCUIT DEVICE
29
Patent #:
8504865
Issue Dt:
08/06/2013
Application #:
11737994
Filing Dt:
04/20/2007
Publication #:
US20080263381
Pub Dt:
10/23/2008
Title:
DYNAMIC PHASE ALIGNMENT
30
Patent #:
7463062
Issue Dt:
12/09/2008
Application #:
11739538
Filing Dt:
04/24/2007
Publication #:
US20070188188
Pub Dt:
08/16/2007
Title:
STRUCTURED INTEGRATED CIRCUIT DEVICE
31
Patent #:
7759971
Issue Dt:
07/20/2010
Application #:
11766575
Filing Dt:
06/21/2007
Publication #:
US20090109765
Pub Dt:
04/30/2009
Title:
SINGLE VIA STRUCTURED IC DEVICE
32
Patent #:
8339844
Issue Dt:
12/25/2012
Application #:
12046626
Filing Dt:
03/12/2008
Publication #:
US20080224260
Pub Dt:
09/18/2008
Title:
PROGRAMMABLE VIAS FOR STRUCTURED ASICS
33
Patent #:
8040739
Issue Dt:
10/18/2011
Application #:
12365019
Filing Dt:
02/03/2009
Publication #:
US20100195419
Pub Dt:
08/05/2010
Title:
CONFIGURABLE WRITE POLICY IN A MEMORY SYSTEM
34
Patent #:
8436700
Issue Dt:
05/07/2013
Application #:
12562812
Filing Dt:
09/18/2009
Publication #:
US20110067982
Pub Dt:
03/24/2011
Title:
MEMS-BASED SWITCHING
35
Patent #:
NONE
Issue Dt:
Application #:
12732436
Filing Dt:
03/26/2010
Publication #:
US20100182044
Pub Dt:
07/22/2010
Title:
PROGRAMMING AND CIRCUIT TOPOLOGIES FOR PROGRAMMABLE VIAS
36
Patent #:
8848479
Issue Dt:
09/30/2014
Application #:
13070894
Filing Dt:
03/24/2011
Publication #:
US20120243285
Pub Dt:
09/27/2012
Title:
MULTIPLE WRITE DURING SIMULTANEOUS MEMORY ACCESS OF A MULTI-PORT MEMORY DEVICE
37
Patent #:
8735857
Issue Dt:
05/27/2014
Application #:
13271679
Filing Dt:
10/12/2011
Publication #:
US20120161093
Pub Dt:
06/28/2012
Title:
VIA-CONFIGURABLE HIGH-PERFORMANCE LOGIC BLOCK ARCHITECTURE
38
Patent #:
8957398
Issue Dt:
02/17/2015
Application #:
13649510
Filing Dt:
10/11/2012
Publication #:
US20140028348
Pub Dt:
01/30/2014
Title:
Via-Configurable High-Performance Logic Block Involving Transistor Chains
39
Patent #:
9024657
Issue Dt:
05/05/2015
Application #:
13649529
Filing Dt:
10/11/2012
Publication #:
US20140103959
Pub Dt:
04/17/2014
Title:
ARCHITECTURAL FLOORPLAN FOR A STRUCTURED ASIC MANUFACTURED ON A 28 NM CMOS PROCESS LITHOGRAPHIC NODE OR SMALLER
40
Patent #:
8629548
Issue Dt:
01/14/2014
Application #:
13649547
Filing Dt:
10/11/2012
Title:
Clock Network Fishbone Architecture for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node
41
Patent #:
8677306
Issue Dt:
03/18/2014
Application #:
13649551
Filing Dt:
10/11/2012
Title:
MICROCONTROLLER CONTROLLED OR DIRECT MODE CONTROLLED NETWORK-FABRIC ON A STRUCTURED ASIC
42
Patent #:
NONE
Issue Dt:
Application #:
13649563
Filing Dt:
10/11/2012
Publication #:
US20140105246
Pub Dt:
04/17/2014
Title:
Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node
43
Patent #:
NONE
Issue Dt:
Application #:
13649584
Filing Dt:
10/11/2012
Publication #:
US20140103985
Pub Dt:
04/17/2014
Title:
Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface
44
Patent #:
RE46474
Issue Dt:
07/11/2017
Application #:
14579337
Filing Dt:
12/22/2014
Title:
Multiple write during simultaneous memory access of a multi-port memory device
45
Patent #:
NONE
Issue Dt:
Application #:
14676497
Filing Dt:
04/01/2015
Publication #:
US20160293541
Pub Dt:
10/06/2016
Title:
STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA LAYERS
46
Patent #:
NONE
Issue Dt:
Application #:
14719430
Filing Dt:
05/22/2015
Publication #:
US20160124899
Pub Dt:
05/05/2016
Title:
MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A FIXED FUNCTION DIE AND USE FOR APPLICATION ACCELERATION
47
Patent #:
9704874
Issue Dt:
07/11/2017
Application #:
14963437
Filing Dt:
12/09/2015
Publication #:
US20170170186
Pub Dt:
06/15/2017
Title:
ROM SEGMENTED BITLINE CIRCUIT
Assignor
1
EASIC CORPORATION
Exec Dt:
03/01/2019
Assignee
1
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
ANGELA MILLER
C/O CPA GLOBAL
900 SECOND AVENUE SOUTH, SUITE 600
MINNEAPOLIS, MN 55402

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