Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 009878/0164 | |
| Pages: | 2 |
| | Recorded: | 04/02/1999 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09182268
|
Filing Dt:
|
10/29/1998
|
|
Title:
|
CHIP LAYOUT FOR IMPLEMENTING ARBITRATED HIGH SPEED SWITCHING ACCESS OF PLURALITIES OF I/O DATA PORTS TO INTERNALLY CACHED DRAM BANKS AND THE LIKE
|
|
|
Assignee
|
|
|
|
|
| 200 NICKERSON ROAD |
| MARLBORO, MASSACHUSETTS 01752 |
|
|
Correspondence name and address
|
| |
RINES AND RINES
|
| |
ROBERT H. RINES
|
| |
81 NORTH STATE STREET
|
| |
CONCORD, NH 03301
|
Search Results as of:
05/30/2024 09:50 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
