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Patent #:
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Issue Dt:
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06/26/1990
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Application #:
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07411424
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Filing Dt:
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09/22/1989
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Title:
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COMPLEMENTARY CIRCUIT AND STRUCTURE WITH COMMON SUBSTRATE
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Patent #:
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Issue Dt:
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02/19/1991
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Application #:
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07416171
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Filing Dt:
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10/02/1989
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Title:
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FIELD CONTROLLED DIODE (FCD) HAVING MOS TRENCH GATES
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Patent #:
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Issue Dt:
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03/12/1991
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Application #:
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07435632
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Filing Dt:
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11/13/1989
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Title:
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SYMMETRICAL BLOCKING HIGH VOLTAGE BREAKDOWN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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06/11/1991
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Application #:
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07447330
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Filing Dt:
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12/07/1989
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Title:
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POWER MOSFET TRANSISTOR CIRCUIT
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Patent #:
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Issue Dt:
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11/06/1990
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Application #:
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07492377
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Filing Dt:
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03/08/1990
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Title:
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GATE ENHANCED RECTIFIER
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Patent #:
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Issue Dt:
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09/15/1992
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Application #:
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07517799
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Filing Dt:
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05/02/1990
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Title:
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HIGH CURRENT HERMETIC PACKAGE
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Patent #:
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Issue Dt:
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08/06/1991
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Application #:
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07545218
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Filing Dt:
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06/26/1990
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Title:
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HERMETICALLY SEALED DIE PACKAGE WITH FLOATING SOURCE
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Patent #:
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Issue Dt:
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02/25/1992
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Application #:
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07592308
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Filing Dt:
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10/03/1990
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Title:
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METHOD OF MAKING A HIGH BREAKDOWN ACTIVE DEVICE STRUCTURE WITH LOW SERIES RESISTANCE
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Patent #:
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Issue Dt:
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03/10/1992
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Application #:
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07609054
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Filing Dt:
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11/06/1990
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Title:
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POWER MOSFET
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Patent #:
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Issue Dt:
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01/07/1992
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Application #:
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07609685
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Filing Dt:
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11/06/1990
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Title:
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POWER MOSFET TRANSISTOR CIRCUIT WITH ACTIVE CLAMP
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Patent #:
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Issue Dt:
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07/28/1992
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Application #:
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07644569
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Filing Dt:
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01/23/1991
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Title:
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SINGLE POWER MOSFET AC POWER SWITCH EMPLOYING MEANS FOR PREVENTING CONDUCTION OF BODY DIODE
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Patent #:
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Issue Dt:
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11/17/1992
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Application #:
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07672243
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Filing Dt:
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03/20/1991
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Title:
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POWER VDMOSFET WITH SCHOTTKY ON LIGHTLY DOPED DRAIN OF LATERAL DRIVER FET
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Patent #:
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Issue Dt:
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03/17/1992
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Application #:
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07672997
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Filing Dt:
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03/21/1991
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Title:
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A COVER WITH THROUGH TERMINALS FOR A HERMETICALLY SEALED ELECTRONIC PACKAGE
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Patent #:
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Issue Dt:
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06/08/1993
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Application #:
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07789901
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Filing Dt:
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11/12/1991
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Title:
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POWER FET HAVING REDUCED THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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09/07/1993
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Application #:
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07797054
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Filing Dt:
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11/25/1991
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Title:
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POWER FET WITH SHIELDED CHANNELS
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Patent #:
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Issue Dt:
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06/21/1994
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Application #:
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07822732
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Filing Dt:
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01/21/1992
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Title:
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POWER FET WITH GATE SEGMENTS COVERING DRAIN REGIONS DISPOSED IN A HEXAGONAL PATTERN
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Patent #:
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Issue Dt:
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03/08/1994
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Application #:
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07973603
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Filing Dt:
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11/09/1992
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Title:
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INTEGRATED HEAT SINK HAVING A SINUOUS FLUID CHANNEL FOR THE THERMAL DISSIPATION OF SEMICONDUCTOR MODULES
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Patent #:
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Issue Dt:
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05/31/1994
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Application #:
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07973709
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Filing Dt:
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11/09/1992
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Title:
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DEVICE AND METHOD FOR IMPROVING CURRENT CARRYING CAPABILITY IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/22/1994
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Application #:
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08051832
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Filing Dt:
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04/26/1993
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Title:
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SEMI-CONDUCTOR CHIP PACKAGING METHOD AND SEMI-CONDUCTOR CHIP HAVING INTERDIGITATED GATE RUNNERS WITH GATE BONDING PADS
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Patent #:
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Issue Dt:
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10/31/1995
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Application #:
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08051839
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Filing Dt:
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04/26/1993
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Title:
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FAST TURN ON SWITCH CIRCUIT WITH PARALLEL MOS CONTROLLED THYRISTOR AND SILICON CONTROLLED RECTIFIER
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Patent #:
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Issue Dt:
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03/21/1995
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Application #:
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08158444
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Filing Dt:
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11/29/1993
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Title:
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MESH GEOMETRY FOR MOS-GATED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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06/13/1995
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Application #:
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08173077
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Filing Dt:
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12/27/1993
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Title:
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APPARATUS AND METHOD FOR INCREASING BREAKDOWN VOLTAGE RUGGEDNESS IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/05/1995
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Application #:
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08177974
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Filing Dt:
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01/06/1994
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Title:
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PACKAGE FOR PARALLEL SUBELEMENT SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/29/1995
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Application #:
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08217801
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Filing Dt:
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01/06/1994
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Title:
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HERMETIC PACKAGE FOR A HIGH POWER SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08223425
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Filing Dt:
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04/05/1994
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Title:
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DEVICE FOR ISOLATING PARALLEL SUB-ELEMENTS WITH REVERSE CONDUCTING DIODE REGIONS
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Patent #:
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Issue Dt:
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06/06/1995
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Application #:
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08246307
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Filing Dt:
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05/19/1994
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Title:
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METHOD OF DOPING A JFET REGION IN A MOS-GATED SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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03/05/1996
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Application #:
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08276464
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Filing Dt:
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07/18/1994
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Title:
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SEMI-CONDUCTOR CHIP HAVING INTERDIGITATED GATE RUNNERS WITH GATE BONDING PADS
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08305435
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Filing Dt:
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09/07/1994
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Title:
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WAFER BONDING FOR POWER DEVICES
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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08310041
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Filing Dt:
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09/22/1994
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Title:
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FET, IGBT AND MCT STRUCTURES TO ENHANCE OPERATING CHARACTERISTICS
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|
|
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Patent #:
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Issue Dt:
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11/21/1995
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Application #:
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08368612
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Filing Dt:
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01/04/1995
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Title:
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METHOE OF FORMING MOS-GATED SEMICONDUCTOR DEVICES HAVING MESH GEOMETRY PATTERN
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|
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Patent #:
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Issue Dt:
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10/03/1995
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Application #:
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08375714
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Filing Dt:
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01/20/1995
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Title:
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COMFET SWITCH AND METHOD
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Patent #:
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Issue Dt:
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11/26/1996
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Application #:
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08462856
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Filing Dt:
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06/05/1995
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Title:
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HERMETIC PACKAGE FOR A HIGH POWER SEMICONDUCTOR DEVICE
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|
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Patent #:
|
|
Issue Dt:
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12/02/1997
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Application #:
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08509590
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Filing Dt:
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07/31/1995
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Title:
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SHORT BURST DIRECT ACQUISITION DIRECT SEQUENCE SPREAD SPECTRUM RECEIVER
|
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Patent #:
|
|
Issue Dt:
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03/09/1999
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Application #:
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08634371
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Filing Dt:
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04/18/1996
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|
Title:
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ASYMMETRIC SNUBBER RESISTOR
|
|
|
|
|
Patent #:
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|
Issue Dt:
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06/23/1998
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Application #:
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08636904
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Filing Dt:
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04/10/1996
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Title:
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TRENCH MOS GATE DEVICE
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08662118
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Filing Dt:
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06/12/1996
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|
Title:
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METHOD FOR FABRICATING A POWER DEVICE
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|
|
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08708712
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Filing Dt:
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09/05/1996
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|
Title:
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METHOD OF FORMING POWER SEMICONDUCTOR DEVICES WITH CONTROLLABLE INTEGRATED BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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08/04/1998
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Application #:
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08712562
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Filing Dt:
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09/11/1996
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|
Title:
|
LOW DISTORTION FEEDBACK IC AMPLIFIER AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
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Application #:
|
08814842
|
Filing Dt:
|
03/11/1997
|
|
Title:
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METHOD OF MAKING MOS-GATED SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
08861562
|
Filing Dt:
|
05/22/1997
|
|
Title:
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ONE MASK, POWER SEMICONDUCTOR DEVICE FABRICATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
08884726
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
SELF-ALIGNED POWER FIELD EFFECT TRANSISTOR IN SILICON CARBIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/1999
|
Application #:
|
08885227
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
BIPOLAR SEMICONDUCTOR POWER CONTROLLING DEVICES WITH HETEROJUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08885877
|
Filing Dt:
|
06/30/1997
|
|
Title:
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METHOD OF MAKING A MOS-GATED SEMICONDUCTOR DEVICE WITH A SINGLE DIFFUSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08885878
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
LIFETIME CONTROL FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
08885879
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
TRENCH CONTACT PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08885921
|
Filing Dt:
|
06/30/1997
|
|
Title:
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A METHOD OF FABRICATING UMOS SEMICONDUCTOR DEVICES USING A SELF-ALIGNED, REDUCED MASK PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
08885922
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
SEMICONDUCTOR STRUCTURES WITH TRENCH CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08944513
|
Filing Dt:
|
10/06/1997
|
|
Title:
|
PROTECTION DEVICE FOR SOLID STATE SWITCHED POWER ELECTORNICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08966867
|
Filing Dt:
|
11/10/1997
|
|
Title:
|
HIGH VOLTAGE MOSFET STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09036815
|
Filing Dt:
|
03/09/1998
|
|
Title:
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ADVANCED METHODS FOR MAKING SEMICONDUCTOR DEVICES BY LOW TEMPERATURE DIRECT BONDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
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Application #:
|
09036838
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Filing Dt:
|
03/09/1998
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|
Title:
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DEVICES FORMABLE BY LOW TEMPERATURE DIRECT BONDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
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Application #:
|
09037723
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Filing Dt:
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03/09/1998
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|
Title:
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METHODS FOR MAKING SEMICONDUCTOR DEVICES BY LOW TEMPERATURE DIRECT BONDING
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|
|
|
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Patent #:
|
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Issue Dt:
|
05/09/2000
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Application #:
|
09040112
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Filing Dt:
|
03/18/1998
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|
Title:
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SEMICONDUCTOR POWER PACK
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|
|
|
|
Patent #:
|
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Issue Dt:
|
07/06/1999
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Application #:
|
09088198
|
Filing Dt:
|
06/01/1998
|
|
Title:
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CIRCUIT AND METHOD FOR PROTECTING FROM OVERCURRENT CONDITIONS AND DETECTING AN OPEN ELECTRICAL LOAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
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Application #:
|
09092334
|
Filing Dt:
|
06/05/1998
|
|
Title:
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METHODS OF FORMING POWER SEMICONDUCTOR DEVICES HAVING MERGED SPLIT-WELL BODY REGIONS THEREIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09096217
|
Filing Dt:
|
06/11/1998
|
|
Title:
|
TRENCH MOS GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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03/06/2001
|
Application #:
|
09098517
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Filing Dt:
|
06/17/1998
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|
Title:
|
HIGH PERFORMANCE HEAT EXCHANGER AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
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Application #:
|
09107273
|
Filing Dt:
|
06/30/1998
|
|
Title:
|
HEAT EXCHANGING CHASSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09107721
|
Filing Dt:
|
06/30/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING REDUCED EFFECTIVE SUBSTRATE RESISTIVITY AND ASSOCIATD METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09108962
|
Filing Dt:
|
07/02/1998
|
|
Title:
|
HIGH VOLTAGE SEMICONDUCTOR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09114769
|
Filing Dt:
|
07/14/1998
|
|
Title:
|
CONDUCTIVITY ENHANCED MOS-GATED SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
09133030
|
Filing Dt:
|
08/12/1998
|
|
Title:
|
FABRICATION OF CONDUCTIVITY ENHANCED MOS-GATED SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09145513
|
Filing Dt:
|
09/02/1998
|
|
Title:
|
METHOD OF MAKING SHALLOW WELL MOSFET STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09167177
|
Filing Dt:
|
10/06/1998
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2001
| | | | |
|
Title:
|
PROCESS FOR FORMING HIGH VOLTAGE JUNCTION TERMINATION EXTENSION OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09167203
|
Filing Dt:
|
10/06/1998
|
|
Title:
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POWER MODULE WITH LOWERED INDUCTANCE AND REDUCED VOLTAGE OVERSHOOTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
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Application #:
|
09203700
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Filing Dt:
|
12/02/1998
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Title:
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CURRENT LIMITED, THERMALLY PROTECTED, POWER DEVICE
|
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Patent #:
|
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Issue Dt:
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06/20/2000
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Application #:
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09255092
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Filing Dt:
|
02/22/1999
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Title:
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SEMICONDUCTOR TRENCH MOS DEVICES
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|
|
|
Patent #:
|
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Issue Dt:
|
02/26/2002
|
Application #:
|
09260411
|
Filing Dt:
|
03/01/1999
|
|
Title:
|
MOS-GATED DEVICE HAVING A BURIED GATE AND PROCESS FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09283531
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
HIGH DENSITY MOS-GATED POWER DEVICE AND PROCESS FOR FORMING SAME
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09283536
|
Filing Dt:
|
04/01/1999
|
|
Publication #:
|
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Pub Dt:
|
05/24/2001
| | | | |
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Title:
|
POWER TRENCH MOS-GATED DEVICE AND PROCESS FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09303270
|
Filing Dt:
|
04/30/1999
|
|
Title:
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POWER MOS DEVICE WITH INCREASED CHANNEL WIDTH AND PROCESS FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09307879
|
Filing Dt:
|
05/10/1999
|
|
Title:
|
PROCESS FOR FORMING MOS-GATED DEVICES HAVING SELF-ALIGNED TRENCHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09314323
|
Filing Dt:
|
05/19/1999
|
|
Title:
|
MOS-GATED POWER DEVICE HAVING EXTENDED TRENCH AND DOPING ZONE AND PROCESS FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09318334
|
Filing Dt:
|
05/25/1999
|
|
Title:
|
TRENCH-GATED DEVICE HAVING TRENCH WALLS FORMED BY SELECTIVE EPITAXIAL GROWTH AND PROCESS FOR FORMING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09324553
|
Filing Dt:
|
06/03/1999
|
|
Title:
|
LOW VOLTAGE DUAL-WELL MOS DEVICE HAVING HIGH RUGGEDNESS, LOW ON-RESISTANCE, AND IMPROVED BODY DIODE REVERSE RECOVERY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
09330437
|
Filing Dt:
|
06/11/1999
|
|
Title:
|
POWER DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09334098
|
Filing Dt:
|
06/16/1999
|
|
Title:
|
POWER MODULE WITH LOWERED INDUCTANCE AND REDUCED VOLTAGE OVERSHOOTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09334835
|
Filing Dt:
|
06/17/1999
|
|
Title:
|
SELF-SUPPORTED ULTRATHIN SILICON WAFER PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09338891
|
Filing Dt:
|
06/23/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE GATE STRUCTURE FOR THERMAL OVERLOAD PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09339356
|
Filing Dt:
|
06/24/1999
|
|
Title:
|
BACKMETAL DRAIN TERMINAL WITH LOW STRESS AND THERMAL RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09344867
|
Filing Dt:
|
06/28/1999
|
|
Title:
|
POTTED TRANSDUCER ARRAY WITH MATCHING NETWORK IN A MULTIPLE PASS CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09344868
|
Filing Dt:
|
06/28/1999
|
|
Title:
|
EDGE TERMINATION FOR SILICON POWER DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09345930
|
Filing Dt:
|
07/01/1999
|
|
Title:
|
POWER SEMICONDUCTOR MOUNTING PACKAGE CONTAINING BALL GRID ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09350575
|
Filing Dt:
|
07/09/1999
|
|
Title:
|
PROCESS FOR FORMING VERTICAL SEMICONDUCTOR DEVICE HAVING INCREASED SOURCE CONTACT AREA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09358625
|
Filing Dt:
|
07/21/1999
|
|
Title:
|
DOUBLY GRADED JUNCTION TERMINATION EXTENSION FOR EDGE PASSIVATION OF SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09450872
|
Filing Dt:
|
11/29/1999
|
|
Title:
|
EMITTER BALLAST RESISTOR WITH ENHANCED BODY EFFECT TO IMPROVE THE SHORT CIRCUIT WITHSTAND CAPABILITY OF POWER DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09498476
|
Filing Dt:
|
02/04/2000
|
|
Title:
|
SEMICONDUCTOR STRUCTURES WITH TRENCH CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09502712
|
Filing Dt:
|
02/11/2000
|
|
Title:
|
MOS-GATED DEVICES WITH ALTERNATING ZONES OF CONDUCTIVITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09525182
|
Filing Dt:
|
03/14/2000
|
|
Title:
|
Power trench transistor device source region formation using silicon spacer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09542561
|
Filing Dt:
|
04/04/2000
|
|
Title:
|
Power device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
09551187
|
Filing Dt:
|
04/17/2000
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING REDUCED EFFECTIVE SUBSTRATE RESISTIVITY AND ASSOCIATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09570009
|
Filing Dt:
|
05/12/2000
|
|
Title:
|
METHOD OF COOLING AN ELECTRONIC POWER MODULE USING A HIGH PERFORMANCE HEAT EXCHANGER INCORPORATING METAL FOAM THEREIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09603605
|
Filing Dt:
|
06/26/2000
|
|
Title:
|
SOFT RECOVERY POWER DIODE AND RELATED METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09624533
|
Filing Dt:
|
07/24/2000
|
|
Title:
|
POWER MOS DEVICE WITH BURIED GATE AND GROOVE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09649815
|
Filing Dt:
|
08/28/2000
|
|
Title:
|
HEAT EXCHANGING CHASSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
09654845
|
Filing Dt:
|
09/01/2000
|
|
Title:
|
POWER SEMICONDUCTOR DEVICE WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING CAPABILITY AND PROCESS FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09663235
|
Filing Dt:
|
09/15/2000
|
|
Title:
|
SIMPLIFIED OZONATOR FOR A SEMICONDUCTOR WAFFER CLEANER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09664024
|
Filing Dt:
|
09/19/2000
|
|
Title:
|
INTEGRATED CIRCUIT DEVICE INCLUDING A DEEP WELL REGION AND ASSOCIATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09665850
|
Filing Dt:
|
09/20/2000
|
|
Title:
|
SELF-ALIGNED PROCESS FOR FABRICATING POWER MOSFET WITH SPACER-SHAPED TERRACED GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09689939
|
Filing Dt:
|
10/12/2000
|
|
Title:
|
MOS-GATED POWER DEVICE HAVING SEGMENTED TRENCH AND EXTENDED DOPING ZONE AND PROCESS FOR FORMING SAME
|
|
