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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Total properties: 18

Patent #:	4897708	Issue Dt:	01/30/1990	Application #:	06887129	Filing Dt:	07/17/1986
Title:	SEMICONDUCTOR WAFER ARRAY

Patent #:	4954875	Issue Dt:	09/04/1990	Application #:	07114633	Filing Dt:	10/28/1987
Title:	SEMICONDUCTOR WAFER ARRAY WITH ELECTRICALLY CONDUCTIVE COMPLIANT MATERIAL

Patent #:	5675180	Issue Dt:	10/07/1997	Application #:	08265081	Filing Dt:	06/23/1994
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	5657206	Issue Dt:	08/12/1997	Application #:	08374421	Filing Dt:	01/19/1995
Title:	A CONDUCTIVE EXPOXY FLIP-CHIP PACKAGE AND METHOD

Patent #:	5698895	Issue Dt:	12/16/1997	Application #:	08376149	Filing Dt:	01/20/1995
Title:	SILICON SEGMENT PROGRAMMING METHOD AND APPARATUS

Patent #:	5661087	Issue Dt:	08/26/1997	Application #:	08476623	Filing Dt:	06/07/1995
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	6134118	Issue Dt:	10/17/2000	Application #:	08834798	Filing Dt:	04/03/1997
Title:	CONDUCTIVE EPOXY FLIP-CHIP PACKAGE AND METHOD

Patent #:	6188126	Issue Dt:	02/13/2001	Application #:	08842448	Filing Dt:	04/24/1997
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	5994170	Issue Dt:	11/30/1999	Application #:	08845654	Filing Dt:	04/25/1997
Title:	SILICON SEGMENT PROGRAMMING METHOD

Patent #:	5936302	Issue Dt:	08/10/1999	Application #:	08845655	Filing Dt:	04/25/1997
Title:	SPEAKER DIAPHRAGM

Patent #:	5837566	Issue Dt:	11/17/1998	Application #:	08847309	Filing Dt:	04/24/1997
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	6098278	Issue Dt:	08/08/2000	Application #:	08917447	Filing Dt:	08/22/1997
Title:	METHOD FOR FORMING CONDUCTIVE EPOXY FLIP-CHIP ON CHIP

Patent #:	6271598	Issue Dt:	08/07/2001	Application #:	08918500	Filing Dt:	08/22/1997
Title:	CONDUCTIVE EPOXY FLIP-CHIP ON CHIP

Patent #:	6124633	Issue Dt:	09/26/2000	Application #:	08918501	Filing Dt:	08/22/1997
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM

Patent #:	5891761	Issue Dt:	04/06/1999	Application #:	08918502	Filing Dt:	08/22/1997
Title:	METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM

Patent #:	6080596	Issue Dt:	06/27/2000	Application #:	08920273	Filing Dt:	08/22/1997
Title:	METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION

Patent #:	6177296	Issue Dt:	01/23/2001	Application #:	09273941	Filing Dt:	03/22/1999
Title:	METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM

Patent #:	6522728	Issue Dt:	02/18/2003	Application #:	09495123	Filing Dt:	02/01/2000
Title:	APPARATUS AND METHOD OF IMPLEMENTING A UNIVERSAL HOME NETWORK ON A CUSTOMER PREMISES ISDN BUS

Assignor

Exec Dt:

08/24/2009

Assignee

10 VICTOR SQUARE, STE. 100

ATTN: FINANCE

SCOTTS VALLEY, CALIFORNIA 95066

Correspondence name and address
	UCC DIRECT
	ATTN: 14080632
	187 WOLF ROAD, SUITE 101
	ALBANY, NY 12205

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