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Patent Assignment Details
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Reel/Frame:010018/0184   Pages: 17
Recorded: 06/15/1999
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 16
1
Patent #:
Issue Dt:
10/12/1993
Application #:
07755111
Filing Dt:
09/05/1991
Title:
BIT LINE AND CELL PLATE CLAMP CIRCUIT FOR A DRAM
2
Patent #:
Issue Dt:
05/31/1994
Application #:
07859670
Filing Dt:
03/30/1992
Title:
LOW POWER DRAM
3
Patent #:
Issue Dt:
02/14/1995
Application #:
07927615
Filing Dt:
08/10/1992
Title:
LATCH-UP IMMUNE CMOS OUTPUT DRIVER
4
Patent #:
Issue Dt:
05/24/1994
Application #:
07940084
Filing Dt:
09/03/1992
Title:
TEMPERATURE COMPENSATED VOLTAGE REFERENCE FOR AND WIDE VOLTAGE RANGES
5
Patent #:
Issue Dt:
08/02/1994
Application #:
07969418
Filing Dt:
10/30/1992
Title:
SENSE AMPLIFIER CLOCK DRIVER
6
Patent #:
Issue Dt:
07/02/1996
Application #:
07983328
Filing Dt:
11/30/1992
Title:
STRESS MODE CIRCUIT FOR AN INTEGRATED CIRCUIT WITH ON-CHIP VOLTAGE DOWN CONVERTER
7
Patent #:
Issue Dt:
07/18/1995
Application #:
07991533
Filing Dt:
12/14/1992
Title:
FUSE PROGRAMMABLE VOLTAGE CONVERTER WITH A SECONDARY TUNING PATH
8
Patent #:
Issue Dt:
08/09/1994
Application #:
08003028
Filing Dt:
01/11/1993
Title:
A HIGH VILTAGE GENERATOR HAVING A SELF-TIMED CLOCK CIRCUIT AND CHARGE PUMP,AND A METHOD THEREFOR
9
Patent #:
Issue Dt:
01/09/1996
Application #:
08003450
Filing Dt:
01/12/1993
Title:
WIDE RANGE POWER SUPPLY FOR INTEGRATED CIRCUITS
10
Patent #:
Issue Dt:
06/14/1994
Application #:
08010342
Filing Dt:
01/28/1993
Title:
LOW-TO-HIGH VOLTAGE TRANSLATOR WITH LATCH-UP IMMUNITY
11
Patent #:
Issue Dt:
07/19/1994
Application #:
08013333
Filing Dt:
02/04/1993
Title:
DRAM VARIABLE ROW SELECT
12
Patent #:
Issue Dt:
01/03/1995
Application #:
08037288
Filing Dt:
03/26/1993
Title:
METHOD AND CIRCUIT FOR IMPROVED TIMING AND NOISE MARGIN IN A DRAM
13
Patent #:
Issue Dt:
10/29/1996
Application #:
08471486
Filing Dt:
06/06/1995
Title:
WIDE RANGE POWER SUPPLY FOR INTEGRATED CIRCUITS
14
Patent #:
Issue Dt:
04/02/1996
Application #:
08472325
Filing Dt:
06/07/1995
Title:
TRANSISTOR PROGRAMMABLE DIVIDER CIRCUIT
15
Patent #:
Issue Dt:
10/21/1997
Application #:
08657637
Filing Dt:
05/30/1996
Title:
CIRCUIT AND METHOD FOR ACCESSING MEMORY CELLS OF A MEMORY DEVICE
16
Patent #:
Issue Dt:
06/09/1998
Application #:
08868179
Filing Dt:
06/03/1997
Title:
BOND PAD OPTION FOR INTEGRATED CIRCUITS
Assignors
1
Exec Dt:
03/02/1999
2
Exec Dt:
03/02/1999
Assignee
1
SCIENCE BASED INDUSTRIAL PARK
3 LI HSIN ROAD 2,
HSIN CHU CITY, TAIWAN
Correspondence name and address
PETER J. COURTURE, ESQ.
993 HIGHLANDS CIRCLE
LOS ALTOS, CA 94024

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