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Reel/Frame:	036327/0190			Pages:	5
		Recorded:	08/14/2015
Attorney Dkt #:	CLVX-1
Conveyance:	MERGER (SEE DOCUMENT FOR DETAILS).

Total properties: 11

Patent #:	10291540	Issue Dt:	05/14/2019	Application #:	14542298	Filing Dt:	11/14/2014
Publication #:	US20160142333	Pub Dt:	05/19/2016
Title:	METHOD AND APPARATUS FOR PERFORMING A WEIGHTED QUEUE SCHEDULING USING A SET OF FAIRNESS FACTORS

Patent #:	10110515	Issue Dt:	10/23/2018	Application #:	14542350	Filing Dt:	11/14/2014
Publication #:	US20160142341	Pub Dt:	05/19/2016
Title:	PACKET SCHEDULING USING HIERARCHICAL SCHEDULING PROCESS

Patent #:	10447608	Issue Dt:	10/15/2019	Application #:	14542393	Filing Dt:	11/14/2014
Publication #:	US20160142331	Pub Dt:	05/19/2016
Title:	PACKET SCHEDULING USING HIERARCHICAL SCHEDULING PROCESS WITH PRIORITY PROPAGATION

Patent #:	9600614	Issue Dt:	03/21/2017	Application #:	14634446	Filing Dt:	02/27/2015
Publication #:	US20160224709	Pub Dt:	08/04/2016
Title:	AUTOMATED FLIP-FLOP INSERTIONS IN PHYSICAL DESIGN WITHOUT PERTURBATION OF ROUTING

Patent #:	9600620	Issue Dt:	03/21/2017	Application #:	14664680	Filing Dt:	03/20/2015
Publication #:	US20160275230	Pub Dt:	09/22/2016
Title:	REPEATER INSERTIONS PROVIDING REDUCED ROUTING PERTURBATION CAUSED BY FLIP-FLOP INSERTIONS

Patent #:	10567273	Issue Dt:	02/18/2020	Application #:	14671900	Filing Dt:	03/27/2015
Publication #:	US20160285744	Pub Dt:	09/29/2016
Title:	METHOD AND APPARATUS FOR BYPASS ROUTING OF MULTICAST DATA PACKETS AND AVOIDING REPLICATION TO REDUCE OVERALL SWITCH LATENCY

Patent #:	9547733	Issue Dt:	01/17/2017	Application #:	14675307	Filing Dt:	03/31/2015
Publication #:	US20160292329	Pub Dt:	10/06/2016
Title:	IDENTIFYING INVERSION ERROR IN LOGIC EQUIVALENCE CHECK

Patent #:	10303626	Issue Dt:	05/28/2019	Application #:	14675342	Filing Dt:	03/31/2015
Publication #:	US20160291932	Pub Dt:	10/06/2016
Title:	APPROACH FOR CHIP-LEVEL FLOP INSERTION AND VERIFICATION BASED ON LOGIC INTERFACE DEFINITION

Patent #:	9792400	Issue Dt:	10/17/2017	Application #:	14675356	Filing Dt:	03/31/2015
Publication #:	US20170068769	Pub Dt:	03/09/2017
Title:	DETERMINATION OF FLIP-FLOP COUNT IN PHYSICAL DESIGN

Patent #:	10824783	Issue Dt:	11/03/2020	Application #:	14675403	Filing Dt:	03/31/2015
Publication #:	US20160292330	Pub Dt:	10/06/2016
Title:	APPROACH FOR LOGIC SIGNAL GROUPING AND RTL GENERATION USING XML

Patent #:	10484311	Issue Dt:	11/19/2019	Application #:	14675450	Filing Dt:	03/31/2015
Publication #:	US20160294735	Pub Dt:	10/06/2016
Title:	METHOD AND APPARATUS FOR USING MULTIPLE LINKED MEMORY LISTS

Assignor

Exec Dt:

04/29/2015

Assignee

2315 N. FIRST STREET

SAN JOSE, CALIFORNIA 95131

Correspondence name and address
	CAVIUM NETWORKS LLC
	2315 N. FIRST STREET
	SAN JOSE, CA 95131

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