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Reel/Frame:038378/0200   Pages: 8
Recorded: 04/07/2016
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 43
1
Patent #:
6661083
Issue Dt:
12/09/2003
Application #:
10081490
Filing Dt:
02/22/2002
Publication #:
US20020163015
Pub Dt:
11/07/2002
Title:
PLASTIC SEMICONDUCTOR PACKAGE
2
Patent #:
6549413
Issue Dt:
04/15/2003
Application #:
10082914
Filing Dt:
02/26/2002
Publication #:
US20020127778
Pub Dt:
09/12/2002
Title:
TAPE BALL GRID ARRAY SEMICONDUCTOR PACKAGE STRUCTURE AND ASSEMBLY PROCESS
3
Patent #:
6967126
Issue Dt:
11/22/2005
Application #:
10608843
Filing Dt:
06/27/2003
Publication #:
US20040043539
Pub Dt:
03/04/2004
Title:
METHOD FOR MANUFACTURING PLASTIC BALL GRID ARRAY WITH INTEGRAL HEATSINK
4
Patent #:
7034387
Issue Dt:
04/25/2006
Application #:
10618933
Filing Dt:
07/14/2003
Publication #:
US20040195667
Pub Dt:
10/07/2004
Title:
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING PROCESSOR AND MEMORY PACKAGE ASSEMBLIES
5
Patent #:
7064426
Issue Dt:
06/20/2006
Application #:
10632549
Filing Dt:
08/02/2003
Publication #:
US20040061212
Pub Dt:
04/01/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
6
Patent #:
6972481
Issue Dt:
12/06/2005
Application #:
10632550
Filing Dt:
08/02/2003
Publication #:
US20040056277
Pub Dt:
03/25/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING STACKED-DIE PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
7
Patent #:
6838761
Issue Dt:
01/04/2005
Application #:
10632551
Filing Dt:
08/02/2003
Publication #:
US20040065963
Pub Dt:
04/08/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES AND HAVING ELECTRICAL SHIELD
8
Patent #:
7053476
Issue Dt:
05/30/2006
Application #:
10632553
Filing Dt:
08/02/2003
Publication #:
US20040063246
Pub Dt:
04/01/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-DOWN FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
9
Patent #:
7205647
Issue Dt:
04/17/2007
Application #:
10632568
Filing Dt:
08/02/2003
Publication #:
US20040063242
Pub Dt:
04/01/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
10
Patent #:
7045887
Issue Dt:
05/16/2006
Application #:
10681583
Filing Dt:
10/08/2003
Publication #:
US20040113254
Pub Dt:
06/17/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE STACKED OVER DIE-UP FLIP-CHIP BALL GRID ARRAY (BGA) PACKAGE
11
Patent #:
7049691
Issue Dt:
05/23/2006
Application #:
10681584
Filing Dt:
10/08/2003
Publication #:
US20040113255
Pub Dt:
06/17/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE AND INCLUDING ADDITIONAL DIE OR STACKED PACKAGE ON SECOND PACKAGE
12
Patent #:
7053477
Issue Dt:
05/30/2006
Application #:
10681734
Filing Dt:
10/08/2003
Publication #:
US20040119152
Pub Dt:
06/24/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED BUMP CHIP CARRIER SECOND PACKAGE
13
Patent #:
6906416
Issue Dt:
06/14/2005
Application #:
10681747
Filing Dt:
10/08/2003
Publication #:
US20040113275
Pub Dt:
06/17/2004
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE STACKED OVER DIE-UP FLIP-CHIP BALL GRID ARRAY (BGA) PACKAGE
14
Patent #:
6933598
Issue Dt:
08/23/2005
Application #:
10681833
Filing Dt:
10/08/2003
Publication #:
US20040124518
Pub Dt:
07/01/2004
Title:
SEMICONDUCTOR STACKED MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE AND ELECTRICALLY SHIELDED FIRST PACKAGE
15
Patent #:
7407080
Issue Dt:
08/05/2008
Application #:
10971202
Filing Dt:
10/22/2004
Publication #:
US20050218188
Pub Dt:
10/06/2005
Title:
WIRE BOND CAPILLARY TIP
16
Patent #:
7306971
Issue Dt:
12/11/2007
Application #:
10976601
Filing Dt:
10/29/2004
Publication #:
US20050208701
Pub Dt:
09/22/2005
Title:
SEMICONDUCTOR CHIP PACKAGING METHOD WITH INDIVIDUALLY PLACED FILM ADHESIVE PIECES
17
Patent #:
8970049
Issue Dt:
03/03/2015
Application #:
11014257
Filing Dt:
12/16/2004
Publication #:
US20050133916
Pub Dt:
06/23/2005
Title:
Multiple chip package module having inverted package stacked over die
18
Patent #:
7101731
Issue Dt:
09/05/2006
Application #:
11059274
Filing Dt:
02/16/2005
Publication #:
US20050148113
Pub Dt:
07/07/2005
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE STACKED OVER DIE-UP FLIP-CHIP BALL GRID ARRAY (BGA) PACKAGE
19
Patent #:
8552551
Issue Dt:
10/08/2013
Application #:
11134845
Filing Dt:
05/20/2005
Publication #:
US20050269676
Pub Dt:
12/08/2005
Title:
ADHESIVE/SPACER ISLAND STRUCTURE FOR STACKING OVER WIRE BONDED DIE
20
Patent #:
7217598
Issue Dt:
05/15/2007
Application #:
11213058
Filing Dt:
08/26/2005
Publication #:
US20060019429
Pub Dt:
01/26/2006
Title:
METHOD FOR MANUFACTURING PLASTIC BALL GRID ARRAY PACKAGE WITH INTEGRAL HEATSINK
21
Patent #:
7208821
Issue Dt:
04/24/2007
Application #:
11252193
Filing Dt:
10/17/2005
Publication #:
US20060081967
Pub Dt:
04/20/2006
Title:
MULTICHIP LEADFRAME PACKAGE
22
Patent #:
7453156
Issue Dt:
11/18/2008
Application #:
11273635
Filing Dt:
11/14/2005
Publication #:
US20060113665
Pub Dt:
06/01/2006
Title:
WIRE BOND INTERCONNECTION
23
Patent #:
7671451
Issue Dt:
03/02/2010
Application #:
11274925
Filing Dt:
11/14/2005
Publication #:
US20060192274
Pub Dt:
08/31/2006
Title:
SEMICONDUCTOR PACKAGE HAVING DOUBLE LAYER LEADFRAME
24
Patent #:
7880313
Issue Dt:
02/01/2011
Application #:
11282293
Filing Dt:
11/17/2005
Publication #:
US20060192295
Pub Dt:
08/31/2006
Title:
SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER
25
Patent #:
7494842
Issue Dt:
02/24/2009
Application #:
11286546
Filing Dt:
11/23/2005
Publication #:
US20070114613
Pub Dt:
05/24/2007
Title:
PROGRAMMABLE NANOTUBE INTERCONNECT
26
Patent #:
7288434
Issue Dt:
10/30/2007
Application #:
11337821
Filing Dt:
01/23/2006
Publication #:
US20060141668
Pub Dt:
06/29/2006
Title:
METHOD FOR MAKING SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE AND INCLUDING ADDITIONAL DIE OR PACKAGE STACKED ON SECOND PACKAGE
27
Patent #:
7247519
Issue Dt:
07/24/2007
Application #:
11337944
Filing Dt:
01/23/2006
Publication #:
US20060158295
Pub Dt:
07/20/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED BUMP CHIP CARRIER SECOND PACKAGE
28
Patent #:
7306973
Issue Dt:
12/11/2007
Application #:
11355920
Filing Dt:
02/16/2006
Publication #:
US20060151867
Pub Dt:
07/13/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING A PROCESSOR AND MEMORY PACKAGE ASSEMBLIES
29
Patent #:
7163842
Issue Dt:
01/16/2007
Application #:
11374383
Filing Dt:
03/13/2006
Publication #:
US20060172459
Pub Dt:
08/03/2006
Title:
METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE STACKED OVER DIE-UP FLIP-CHIP BALL GRID ARRAY (BGA)
30
Patent #:
7279361
Issue Dt:
10/09/2007
Application #:
11374468
Filing Dt:
03/13/2006
Publication #:
US20060172463
Pub Dt:
08/03/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
31
Patent #:
7682873
Issue Dt:
03/23/2010
Application #:
11374472
Filing Dt:
03/13/2006
Publication #:
US20060170091
Pub Dt:
08/03/2006
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-DOWN FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
32
Patent #:
8623704
Issue Dt:
01/07/2014
Application #:
11530841
Filing Dt:
09/11/2006
Publication #:
US20070015314
Pub Dt:
01/18/2007
Title:
ADHESIVE/SPACER ISLAND STRUCTURE FOR MULTIPLE DIE PACKAGE
33
Patent #:
8030134
Issue Dt:
10/04/2011
Application #:
11536424
Filing Dt:
09/28/2006
Publication #:
US20070018296
Pub Dt:
01/25/2007
Title:
STACKED SEMICONDUCTOR PACKAGE HAVING ADHESIVE/SPACER STRUCTURE AND INSULATION
34
Patent #:
7351610
Issue Dt:
04/01/2008
Application #:
11622993
Filing Dt:
01/12/2007
Publication #:
US20070111388
Pub Dt:
05/17/2007
Title:
METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING A SECOND PACKAGE SUBSTRATE WITH AN EXPOSED METAL LAYER WIRE BONDED TO A FIRST PACKAGE SUBSTRATE
35
Patent #:
7638363
Issue Dt:
12/29/2009
Application #:
11684265
Filing Dt:
03/09/2007
Publication #:
US20070155053
Pub Dt:
07/05/2007
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
36
Patent #:
7436048
Issue Dt:
10/14/2008
Application #:
11686010
Filing Dt:
03/14/2007
Publication #:
US20070152308
Pub Dt:
07/05/2007
Title:
MULTICHIP LEADFRAME PACKAGE
37
Patent #:
8030756
Issue Dt:
10/04/2011
Application #:
11697433
Filing Dt:
04/06/2007
Publication #:
US20070176289
Pub Dt:
08/02/2007
Title:
PLASTIC BALL GRID ARRAY PACKAGE WITH INTEGRAL HEATSINK
38
Patent #:
7732254
Issue Dt:
06/08/2010
Application #:
11744182
Filing Dt:
05/03/2007
Publication #:
US20080036096
Pub Dt:
02/14/2008
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-UP FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
39
Patent #:
8143100
Issue Dt:
03/27/2012
Application #:
11849112
Filing Dt:
08/31/2007
Publication #:
US20070292990
Pub Dt:
12/20/2007
Title:
METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
40
Patent #:
7749807
Issue Dt:
07/06/2010
Application #:
11953857
Filing Dt:
12/10/2007
Publication #:
US20090027863
Pub Dt:
01/29/2009
Title:
METHOD OF FABRICATING A SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING A PROCESSOR AND MEMORY PACKAGE ASSEMBLIES
41
Patent #:
7745322
Issue Dt:
06/29/2010
Application #:
12032159
Filing Dt:
02/15/2008
Publication #:
US20080135997
Pub Dt:
06/12/2008
Title:
WIRE BOND INTERCONNECTION
42
Patent #:
7935572
Issue Dt:
05/03/2011
Application #:
12767693
Filing Dt:
04/26/2010
Publication #:
US20100200966
Pub Dt:
08/12/2010
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-UP FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
43
Patent #:
7986047
Issue Dt:
07/26/2011
Application #:
12783039
Filing Dt:
05/19/2010
Publication #:
US20100225008
Pub Dt:
09/09/2010
Title:
WIRE BOND INTERCONNECTION
Assignor
1
STATS CHIPPAC LTD
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTE
5 YISHUN STREET 23
SINGAPORE, SINGAPORE
Correspondence name and address
EDWARD J. MAYLE
1850 K STREET, N.W.
SUITE 1100
WASHINGTON, DC 20006

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