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08/12/2003
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09639840
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08/16/2000
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05/06/2003
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09639841
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08/16/2000
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Title:
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PROGRAMMABLE AUTO-CONVERTING ANAALOG TO DIGITAL CONVERTSION MODULE
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03/19/2002
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09650561
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08/30/2000
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04/06/2004
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09650774
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08/29/2000
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Title:
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CONTENTION-BASED METHODS FOR GENERATING REDUCED NUMBER OF INTERRUPTS
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07/02/2002
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09661681
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09/14/2000
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BIAS GENERATING CIRCUIT FOR USE WITH AN OSCILLATING CIRCUIT IN AN INTEGRATED CIRCUIT CHARGE PUMP
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04/01/2003
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09675355
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09/29/2000
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Title:
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COMPARATOR PROGRAMMABLE FOR HIGH-SPEED OR LOW-POWER OPERATION
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02/04/2003
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09675356
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09/29/2000
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INPUT VOLTAGE OFFSET CALIBRATION OF AN ANALOG DEVICE USING A MICROCONTROLLER
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10/01/2002
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09676389
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09/29/2000
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AUTO-CALIBRATION CIRCUIT TO MINIMIZE INPUT OFFSET VOLTAGE IN AN INTEGRATED CIRCUIT ANALOG INPUT DEVICE
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05/18/2004
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09680679
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10/06/2000
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Title:
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A CLOCK RECOVERY UNIT WHICH USES A DETECTED FREQUENCY DIFFERENCE SIGNAL TO HELP ESTABLISH PHASE LOCK BETWEEN A TRANSMITTED DATA SIGNAL AND A RECOVERED CLOCK SIGNAL
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08/31/2004
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09680834
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10/06/2000
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DUAL-CHANNEL SCSI CHIPS AND METHODS FOR CONFIGURING SEPARATE INTEROPERABILITY OF EACH CHANNEL OF THE SCSI CHIP
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09/05/2006
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09687244
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10/12/2000
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METHOD AND APPARATUS FOR ESTABLISHING A PROFILE TABLE FOR HOST BUS ADAPTERS
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10/16/2001
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09687391
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10/13/2000
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Title:
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Shunt resistance device for monitoring battery state of charge
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08/10/2004
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09687623
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10/12/2000
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METHOD AND APPARATUS FOR A LAYER STRUCTURE DIRECTORY FOR COMMON HARDWARE INTERFACE MODULES
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09/05/2006
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09687699
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10/12/2000
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METHOD AND APPARATUS FOR DEVICE DISCOVERY
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06/08/2004
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09690120
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10/12/2000
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METHOD AND APPARATUS FOR ADDRESS MAPPING
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06/10/2003
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09691375
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10/18/2000
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Title:
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PROCESSOR ARCHITECTURE SCHEME WHICH USES VIRTUAL ADDRESS REGISTERS TO IMPLEMENT DIFFERENT ADDRESSING MODES AND METHOD THEREFOR
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04/20/2004
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09691579
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10/18/2000
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Title:
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CONTROLLER FAULT RECOVERY SYSTEM FOR A DISTRIBUTED FILE SYSTEM
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01/21/2003
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09695966
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10/25/2000
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TIME CONSTRAINED SENSOR DATA RETRIEVAL SYSTEM AND METHOD
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06/01/2004
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09697119
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10/27/2000
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Title:
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ADAPTIVE PHASE SHIFT FILTRATION OF POINTER JUSTIFICATION JITTER IN SYNCHRONOUS-PLESIOSYNCHRONOUS SIGNAL DESYNCHRONIZATION
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02/24/2004
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09698891
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10/27/2000
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DATA COMMUNICATION INTERFACE BETWEEN HOST AND SLAVE PROCESSORS
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02/12/2002
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09709654
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11/13/2000
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Controlled analogue driver system
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03/25/2003
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09713513
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11/14/2000
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METHOD OF FORMING SHALLOW TRENCH ISOLATION IN A SILICON WAFER
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06/08/2004
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09714524
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11/17/2000
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METHOD AND DEVICE FOR CONTROLLING THE THICKNESS OF A LAYER OF AN INTEGRATED CIRCUIT IN REAL TIME
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06/17/2003
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09715847
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11/17/2000
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ACTIVELY-CONTROLLABLE OPTICAL SWITCHES BASED ON OPTICAL POSITION SENSING AND APPLICATIONS IN OPTICAL SWITCHING ARRAYS
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04/30/2002
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09718650
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11/21/2000
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Title:
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TIMING INDEPENDENT CURRENT COMPARISON AND SELF-LATCHING DATA CIRCUIT
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04/02/2002
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09721186
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11/20/2000
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Title:
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INTEGRATED CIRCUIT LAYOUT FOR LF - SIGNAL ACQUISITION IN THE CASE OF CONTACTLESS DATA TRANSMISSION
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05/20/2003
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09726690
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11/29/2000
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05/30/2002
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POWER ON CIRCUIT FOR GENERATING RESET SIGNAL
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11/12/2002
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09728190
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12/01/2000
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07/25/2002
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Title:
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INDUCTIVELY TUNABLE ANTENNA FOR A RADIO FREQUENCY IDENTIFICATION TAG
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08/10/2004
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09728191
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12/01/2000
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06/06/2002
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MODULATED INPUT SIGNAL FILTER
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07/23/2002
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09728217
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12/01/2000
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06/06/2002
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Title:
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Radio frequency identification tag on a single layer substrate
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03/18/2003
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09731381
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12/06/2000
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06/06/2002
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CONFIGURABLE OPERATIONAL AMPLIFIER AS A MICROCONTROLLER PERIPHERAL
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01/11/2005
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09734632
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12/11/2000
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08/16/2001
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PROCEDURE FOR INCREASING THE MANIPULATION SECURITY FOR A BI-DIRECTIONAL CONTACTLESS DATA TRANSMISSION
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02/10/2004
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09742861
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12/20/2000
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07/05/2001
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INTEGRATED CIRCUIT PROVIDED WITH MEAND FOR CALIBRATING AN ELECTRIC MODULE AND METHOD FOR CALIBRATING AN ELECTRIC MODULE OF AN INTEGRATED CIRCUIT
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07/27/2004
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09745034
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12/20/2000
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METHOD AND SYSTEM FOR FLOW CONTROL DURING THE DATA OUT PHASE OF THE PACKETIZED SCSI PROTOCOL
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12/12/2006
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09752504
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12/27/2000
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METHODS FOR MANAGING HOST ADAPTER SETTINGS
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07/06/2010
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09756680
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01/10/2001
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09/12/2002
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SYSTEM INTERFACE FOR CELL AND/OR PACKET TRANSFER
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02/17/2004
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09764169
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01/16/2001
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07/18/2002
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INPUT/OUTPUT CONTINUITY TEST MODE CIRCUIT
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06/03/2003
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09765093
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01/17/2001
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07/18/2002
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METHOD AND APPARATUS USING DIRECTIONAL ANTENNA OR LEARNING MODES FOR TIRE INFLATION PRESSURE MONITORING AND LOCATION DETERMINATION
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10/15/2002
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09765094
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01/17/2001
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07/18/2002
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TIRE INFLATION PRESSURE MONITORING AND LOCATION DETERMINING METHOD AND APPARATUS
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11/02/2004
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09766094
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01/19/2001
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09/26/2002
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METHOD AND APPARATUS FOR SIGNAL FREQUENCY DECODING WITHOUT AN ANALOG BANDPASS FILTER
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07/27/2004
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09768859
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01/23/2001
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METHOD AND APPARATUS FOR INTELLIGENT FAILOVER IN A MULTI-PATH SYSTEM
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11/23/2004
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01/23/2001
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METHOD AND APPARATUS FOR A SEGREGATED INTERFACE FOR PARAMETER CONFIGURATION IN A MULTI-PATH FAILOVER SYSTEM
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10/05/2004
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09768957
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01/23/2001
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INTELLIGENT LOAD BALANCING FOR A MULTI-PATH STORAGE SYSTEM
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07/08/2003
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09768984
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01/23/2001
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09/06/2001
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MEMORY CELL WITH SELF-ALIGNED FLOATING GATE AND SEPARATE SELECT GATE, AND FABRICATION PROCESS
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08/03/2004
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09769679
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01/25/2001
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07/25/2002
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APPARATUS FOR SECURE STORAGE OF VEHICLE ODOMETER VALUES AND METHOD THEREFOR
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09/24/2002
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01/31/2001
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MICROCONTROLLER WITH INTEGRAL SWITCH MODE POWER SUPPLY CONTROLLER
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04/22/2003
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02/05/2001
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08/08/2002
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MULTI-CHANNEL CLOCK RECOVERY CIRCUIT
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02/19/2002
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09785121
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02/16/2001
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11/09/2004
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03/02/2001
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I/O SUBSYSTEM TOPOLOGY DISCOVERY METHOD
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06/22/2004
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09798275
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03/02/2001
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06/15/2004
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03/02/2001
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10/01/2002
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03/05/2001
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10/03/2002
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SPLIT COMMON SOURCE ON EEPROM ARRAY
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10/15/2002
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09802184
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03/08/2001
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11/08/2001
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REDUCTION OF DATA DEPENDENT POWER SUPPLY NOISE WHEN SENSING THE STATE OF A MEMORY CELL
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05/07/2002
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03/12/2001
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11/08/2001
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DIGITALLY SWITCHED IMPEDANCE HAVING IMPROVED LINEARITY AND SETTLING TIME
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01/17/2006
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03/16/2001
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09/19/2002
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ON-CHIP METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR CIRCUITS
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06/04/2002
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09816801
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03/23/2001
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INDEPENDENT ASYNCHRONOUS BOOT BLOCK FOR SYNCHRONOUS NON-VOLATILE MEMORY DEVICES
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06/18/2002
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03/27/2001
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HIGH VOLTAGE MULTIPURPOSE INPUT/OUTPUT CIRCUIT
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08/06/2002
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09823032
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03/29/2001
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02/14/2002
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METHOD OF SELF-ALIGNING A FLOATING GATE TO A CONTROL GATE AND TO AN ISOLATION IN AN ELECTRICALLY ERASABLE AND PROGRAMMABLE MEMORY CELL, AND A CELL MADE THEREBY
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06/03/2003
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04/04/2001
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10/25/2001
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CURRENT MEASURING APPARATUS FOR BATTERY
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08/16/2005
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04/05/2001
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10/17/2002
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EVENT DETECTION WITH A DIGITAL PROCESSOR
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01/21/2003
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04/16/2001
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10/04/2001
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AMPLIFIER PHASE REVERSAL SUPPRESSION
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02/15/2005
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04/20/2001
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12/05/2002
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WIRELESS IC INTERCONNECTION METHOD AND SYSTEM
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07/15/2003
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09842612
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Filing Dt:
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04/26/2001
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Publication #:
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Pub Dt:
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12/27/2001
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Title:
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PROCESS FOR REDUCING THE DECAY AND TRANSIENT TIMES OF OSCILLATING CIRCUITS
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09846018
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Filing Dt:
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04/30/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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IMPROVED LAYOUT TECHNIQUE FOR A CAPACITOR ARRAY USING CONTINUOUS UPPER ELECTRODES
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09850214
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Filing Dt:
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05/07/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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METHOD FOR POWERING DOWN UNUSED CONFIGURATION BITS TO MINIMIZE POWER CONSUMPTION
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09850530
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Filing Dt:
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05/07/2001
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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PAD CALIBRATION CIRCUIT WITH ON-CHIP RESISTOR
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09856330
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Filing Dt:
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05/18/2001
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Title:
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DIGITAL-TO-ANALOGUE CONVERTER
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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09859570
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Filing Dt:
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05/16/2001
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Publication #:
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Pub Dt:
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11/29/2001
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Title:
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APPARATUS AND METHOD FOR PROGRAMMABLE CONTROL OF LASER DIODE MODULATION AND OPERATING POINT
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09860706
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Filing Dt:
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05/18/2001
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Title:
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CONTROL CIRCUIT FOR A NON-VOLATILE MEMORY ARRAY FOR CONTROLLING THE RAMP RATE OF HIGH VOLTAGE APPLIED TO THE MEMORY CELLS AND TO LIMIT THE CURRENT DRAWN THEREFROM
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09862078
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Filing Dt:
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05/21/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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FLASH MEMORY CELL WITH CONTACTLESS BIT LINE, AND PROCESS OF FABRICATION
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09866110
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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METHOD AND APPARATUS FOR SCALABLE ERROR CORRECTION CODE GENERATION PERFORMANCE
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09870445
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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MODULO ADDRESSING BASED ON ABSOLUTE OFFSET
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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09870447
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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VARIABLE CYCLE INTERRUPT DISABLING
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Patent #:
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Issue Dt:
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07/29/2003
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Application #:
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09870448
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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DYNAMICALLY RECONFIGURABLE DATA SPACE
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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09870454
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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CONFIGURATION FUSES FOR SETTING PWM OPTIONS
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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09870460
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
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Title:
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MODIFIED HARVARD ARCHITECTURE PROCESSOR HAVING DATA MEMORY SPACE MAPPED TO PROGRAM MEMORY SPACE WITH ERRONEOUS EXECUTION PROTECTION
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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09870461
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
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Title:
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STICKY Z BIT
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Patent #:
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Issue Dt:
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08/30/2005
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Application #:
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09870626
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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PROCESSOR WITH DUAL-DEADTIME PULSE WIDTH MODULATION GENERATOR
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09870648
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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MODIFIED HARVARD ARCHITECTURE PROCESSOR HAVING DATA MEMORY SPACE MAPPED TO PROGRAM MEMORY SPACE
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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09870649
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
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Title:
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EUCLIDEAN DISTANCE INSTRUCTIONS
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09870650
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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PROCESSOR WITH PULSE WIDTH MODULATION GENERATOR WITH FAULT INPUT PRIORITIZATION
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Patent #:
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Issue Dt:
|
10/04/2005
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Application #:
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09870711
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
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Title:
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MAXIMALLY NEGATIVE SIGNED FRACTIONAL NUMBER MULTIPLICATION
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Patent #:
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Issue Dt:
|
03/28/2006
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Application #:
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09870772
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
|
07/03/2003
| | | | |
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Title:
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REDUCED POWER OPTION
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Patent #:
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Issue Dt:
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12/16/2008
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Application #:
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09870944
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
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Title:
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DUAL MODE ARITHMETIC SATURATION PROCESSING
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Patent #:
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Issue Dt:
|
02/11/2003
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Application #:
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09877353
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Filing Dt:
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06/07/2001
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Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
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Title:
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SENSE AMPLIFIER WITH IMPROVED LATCHING
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Patent #:
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Issue Dt:
|
09/20/2005
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Application #:
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09878054
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Filing Dt:
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06/06/2001
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Publication #:
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Pub Dt:
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02/21/2002
| | | | |
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Title:
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CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
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Patent #:
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Issue Dt:
|
04/29/2003
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Application #:
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09880545
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Filing Dt:
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06/12/2001
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Publication #:
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Pub Dt:
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01/24/2002
| | | | |
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Title:
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CHARGE PUMP REGULATOR WITH LOAD CURRENT CONTROL
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Patent #:
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Issue Dt:
|
09/28/2004
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Application #:
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09884270
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Filing Dt:
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06/19/2001
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
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Title:
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SPARSE BYTE ENABLE INDICATOR FOR HIGH SPEED MEMORY ACCESS ARBITRATION METHOD AND APPARATUS
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Patent #:
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Issue Dt:
|
08/24/2004
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Application #:
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09891518
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Filing Dt:
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06/27/2001
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Publication #:
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Pub Dt:
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03/20/2003
| | | | |
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Title:
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JITTER TOLERANCE IMPROVEMENT BY PHASE FILTRATION IN FEED-FORWARD DATA RECOVERY SYSTEMS
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Patent #:
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Issue Dt:
|
05/18/2004
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Application #:
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09892807
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Filing Dt:
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06/26/2001
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|
Publication #:
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Pub Dt:
|
08/07/2003
| | | | |
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Title:
|
LIMITING AMPLIFIER MODULATOR DRIVER
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Patent #:
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|
Issue Dt:
|
01/07/2003
|
Application #:
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09898582
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Filing Dt:
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07/02/2001
|
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Publication #:
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Pub Dt:
|
03/28/2002
| | | | |
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Title:
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ARRAY ARCHITECTURE AND OPERATING METHODS FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
|
09/24/2002
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Application #:
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09903919
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Filing Dt:
|
07/12/2001
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Title:
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METHOD AND APPARATUS FOR SENSING A MEMORY SIGNAL FROM A SELECTED MEMORY CELL OF A MEMORY DEVICE
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Patent #:
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Issue Dt:
|
12/03/2002
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Application #:
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09904160
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Filing Dt:
|
07/11/2001
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Title:
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BITLINE PRECHARGE MATCHING
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Patent #:
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Issue Dt:
|
09/12/2006
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Application #:
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09904704
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Filing Dt:
|
07/12/2001
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
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Title:
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METHOD AND APPARATUS FOR IMPROVED RAID 1 WRITE PERFORMANCE IN LOW COST SYSTEMS
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Patent #:
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Issue Dt:
|
03/08/2005
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Application #:
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09910580
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Filing Dt:
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07/20/2001
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Title:
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METHODS FOR OPTIMIZING MEMORY RESOURCES DURING INITIALIZATION ROUTINES OF A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
|
09/30/2003
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Application #:
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09916423
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
|
10/03/2002
| | | | |
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Title:
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A SELF-ALIGNED FLOATING GATE POLY FOR A FLASH E2PROM CELL
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09916555
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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03/21/2002
| | | | |
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Title:
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A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH LOW RESISTANCE SOURCE REGIONS AND HIGH SOURCE COUPLING
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Patent #:
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Issue Dt:
|
11/22/2005
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Application #:
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09916618
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
|
10/10/2002
| | | | |
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Title:
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SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH VERTICAL CONTROL GATE SIDEWALLS AND INSULATION SPACERS
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09916619
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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03/21/2002
| | | | |
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Title:
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A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH CONTROL GATE SPACER PORTIONS
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Patent #:
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Issue Dt:
|
09/30/2003
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Application #:
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09917023
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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03/21/2002
| | | | |
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Title:
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SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH CONTROL GATES PROTRUDING PORTIONS, AND A MEMORY ARRAY MADE THEREBY
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|
