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03/11/2004
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10/19/2004
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10/07/2004
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08/30/2005
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04/07/2003
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10/07/2004
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03/13/2007
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04/07/2003
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10/07/2004
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10/10/2006
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04/11/2003
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10/14/2004
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09/21/2004
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04/10/2003
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07/15/2004
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03/14/2006
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04/21/2003
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01/22/2004
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03/07/2006
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04/23/2003
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10/28/2004
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03/09/2004
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04/25/2003
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07/19/2005
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04/25/2003
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10/28/2004
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02/28/2006
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04/25/2003
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02/26/2004
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11/20/2007
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04/29/2003
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03/22/2005
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04/29/2003
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02/12/2004
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02/08/2005
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05/02/2003
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11/04/2004
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04/21/2015
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11/04/2004
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12/26/2006
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05/10/2003
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10/14/2004
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07/27/2004
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05/13/2003
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07/29/2008
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05/21/2003
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11/25/2004
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09/07/2004
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11/13/2007
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05/23/2003
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12/04/2003
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11/23/2004
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05/30/2003
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12/02/2004
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02/15/2005
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12/02/2004
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02/20/2007
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06/02/2003
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12/16/2004
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11/23/2004
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12/09/2004
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01/11/2005
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12/09/2004
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07/29/2004
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06/16/2005
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04/01/2008
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11/30/2006
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09/16/2008
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06/25/2003
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11/09/2004
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09/05/2006
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06/26/2003
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05/15/2007
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08/16/2005
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07/09/2003
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02/26/2004
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01/31/2006
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07/11/2003
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01/15/2004
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03/11/2008
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07/14/2003
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04/29/2004
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12/26/2006
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07/14/2003
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03/29/2005
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09/09/2004
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11/06/2007
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07/28/2003
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01/29/2004
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01/31/2006
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07/28/2003
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02/03/2005
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05/10/2005
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08/04/2003
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02/10/2005
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01/31/2006
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08/11/2003
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02/17/2005
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10/17/2006
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08/14/2003
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03/14/2006
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08/14/2003
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02/17/2005
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03/01/2005
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08/14/2003
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02/17/2005
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08/17/2004
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08/14/2003
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06/29/2004
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08/15/2003
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10/26/2004
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08/15/2003
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12/21/2004
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08/15/2003
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03/22/2005
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08/14/2003
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02/17/2005
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03/14/2006
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08/14/2003
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02/17/2005
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08/09/2005
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08/14/2003
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02/17/2005
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A MULTI-BIT ROM CELL, FOR STORING ONE OF N>4 POSSIBLE STATES AND HAVING BI-DIRECTIONAL READ, AN ARRAY OF SUCH CELLS.
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09/07/2004
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08/15/2003
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07/24/2007
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08/18/2003
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03/17/2005
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10/05/2004
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08/28/2003
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06/14/2005
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08/28/2003
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03/03/2005
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Title:
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SELF-ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED FLOATING GATE, AND A MEMORY ARRAY MADE THEREBY
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10656071
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Filing Dt:
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09/04/2003
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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METHOD OF MAKING NONVOLATILE TRANSISTOR PAIRS WITH SHARED CONTROL GATE
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10656486
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Filing Dt:
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09/04/2003
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Title:
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PHASE CHANGE MEMORY DEVICE EMPLOYING THERMALLY INSULATING VOIDS, AND A METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10656668
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Filing Dt:
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09/04/2003
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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MEMORY DEVICE WITH DISCRETE LAYERS OF PHASE CHANGE MEMORY MATERIAL
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10659226
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Filing Dt:
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09/09/2003
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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UNIFIED MULTILEVEL CELL MEMORY
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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10666142
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Filing Dt:
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09/17/2003
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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REGENERATIVE CLOCK REPEATER
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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10669040
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Filing Dt:
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09/22/2003
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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SOURCE SYNCHRONOUS CDMA BUS INTERFACE
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10669081
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Filing Dt:
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09/23/2003
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Publication #:
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Pub Dt:
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07/08/2004
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Title:
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FRONT SIDE ILLUMINATED PHOTODIODE WITH BACKSIDE BUMP
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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10670619
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Filing Dt:
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09/25/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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Q-QUENCHING SUPER-REGENERATIVE RECEIVER
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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10671200
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Filing Dt:
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09/25/2003
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Publication #:
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Pub Dt:
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12/30/2004
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Title:
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LOW VOLTAGE CIRCUIT FOR INTERFACING WITH HIGH VOLTAGE ANALOG SIGNALS
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10677123
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10677449
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Filing Dt:
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10/02/2003
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Publication #:
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Pub Dt:
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04/07/2005
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Title:
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SWITCHED-CAPACITOR SAMPLE/HOLD HAVING REDUCED AMPLIFIER SLEW-RATE AND SETTLING TIME REQUIREMENTS
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10677452
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Filing Dt:
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10/02/2003
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Title:
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DIMMABLE ELECTROLUMANESCENT LAMP DRIVERS AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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10680355
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Filing Dt:
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10/06/2003
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Publication #:
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Pub Dt:
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04/07/2005
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Title:
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SEMICONDUCTOR DEVICE WITH A TOROIDAL-LIKE JUNCTION
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10685629
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Filing Dt:
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10/15/2003
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Title:
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METHOD FOR INTEGRATING NON-VOLATILE MEMORY WITH HIGH-VOLTAGE AND LOW-VOLTAGE LOGIC IN A SALICIDE PROCESS
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10685752
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
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04/14/2005
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Title:
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SUSPEND-RESUME PROGRAMMING METHOD FOR FLASH MEMORY
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10685957
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
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04/14/2005
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Title:
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GROUP ERASING SYSTEM FOR FLASH ARRAY WITH MULTIPLE SECTORS
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10690082
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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METHOD AND SYSTEM FOR ENHANCING THE ENDURANCE OF MEMORY CELLS
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10690204
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH LOW RESISTANCE SOURCE REGIONS AND HIGH SOURCE COUPLING
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10693067
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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LANDING PAD FOR USE AS A CONTACT TO A CONDUCTIVE SPACER
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10693285
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Filing Dt:
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10/23/2003
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Title:
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PROGRAMMABLE LOGIC DEVICE PARTITIONING METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT PROTOTYPING
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10697133
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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CHARGE TRANSFER CAPACITIVE POSITION SENSOR
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10701216
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Filing Dt:
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11/04/2003
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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METHOD OF COMMUNICATION USING AN ENCODER MICROCHIP AND A DECODER MICROCHIP
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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10712710
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Filing Dt:
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11/12/2003
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Title:
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METHODS FOR EXPANSIVE NETBOOT
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Patent #:
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Issue Dt:
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12/11/2012
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Application #:
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10712711
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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SIMULATION OF COMPLEX SYSTEM ARCHITECTURE
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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10714243
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Filing Dt:
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11/13/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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STACKED GATE MEMORY CELL WITH ERASE TO GATE, ARRAY, AND METHOD OF MANUFACTURING
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10717149
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Filing Dt:
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11/18/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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METHOD OF FORMING A LOW VOLTAGE GATE OXIDE LAYER AND TUNNEL OXIDE LAYER IN AN EEPROM CELL
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Patent #:
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Issue Dt:
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12/11/2007
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Application #:
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10718624
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Filing Dt:
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11/24/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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PACKET TYPE ARBITRATOR IN WLAN AND CORRESPONDING ARBITRATING METHOD
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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10718748
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Filing Dt:
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11/21/2003
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Title:
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EMBEDDED MEMORY WITH SECURITY ROW LOCK PROTECTION
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10721355
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Filing Dt:
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11/26/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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METHOD AND SYSTEM FOR CHANNEL ESTIMATION IN WLAN
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10722819
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Filing Dt:
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11/25/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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SERIAL PERIPHERAL INTERFACE (SPI) APPARATUS WITH WRITE BUFFER FOR IMPROVING DATA THROUGHPUT
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10723103
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Filing Dt:
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11/26/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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CUSTOMIZED MICROELECTRONIC DEVICE AND METHOD FOR MAKING CUSTOMIZED ELECTRICAL INTERCONNECTIONS
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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10725183
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Filing Dt:
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12/01/2003
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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FLEXIBLE ADAPTATION ENGINE FOR ADAPTIVE TRANSVERSAL FILTERS
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Patent #:
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Issue Dt:
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08/30/2005
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Application #:
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10729605
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Filing Dt:
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12/05/2003
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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MEMORY DEVICE AND METHOD OF OPERATING SAME
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10732998
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Filing Dt:
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12/11/2003
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Publication #:
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Pub Dt:
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09/16/2004
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Title:
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CACHE MEMORY ARCHITECTURE AND ASSOCIATED MICROPROCESSOR DESIGN
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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10733152
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Filing Dt:
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12/10/2003
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Title:
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METHOD AND APPARATUS FOR VENDOR-SPECIFIC DEVICE COMMUNICATION
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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10736372
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Filing Dt:
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12/15/2003
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Publication #:
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Pub Dt:
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06/16/2005
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Title:
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TIME SIGNAL RECEIVER AND DECODER
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10737676
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Filing Dt:
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12/15/2003
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Title:
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EEPROM ARCHITECTURE AND PROGRAMMING PROTOCOL
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10737689
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Filing Dt:
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12/15/2003
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Publication #:
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Pub Dt:
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07/01/2004
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Title:
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SEEK WINDOW VERIFY PROGRAM SYSTEM AND METHOD FOR A MULTILEVEL NON-VOLATILE MEMORY INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10740331
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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DIGITALLY CONTROLLED TUNER CIRCUIT
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Patent #:
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Issue Dt:
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10/06/2009
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Application #:
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10740971
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Filing Dt:
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12/19/2003
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Title:
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SYSTEM AND METHOD FOR AUTHENTICATION OF EMBEDDED RAID ON A MOTHERBOARD
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Patent #:
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Issue Dt:
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03/10/2009
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Application #:
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10741234
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Filing Dt:
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12/19/2003
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Title:
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SYSTEM AND METHOD FOR AUTHENTICATION OF EMBEDDED RAID ON A MOTHERBOARD HAVING INPUT/OUTPUT PROCESSOR
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10741986
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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HIGH FREQUENCY POWER DETECTOR WITH DBM-LINEAR CHARACTERISTIC AND METHOD OF REGULATING THE POWER OF AN ELECTRICAL HF-OSCILLATION
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10748540
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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06/30/2005
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Title:
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LOW VOLTAGE CMOS BANDGAP REFERENCE
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10749342
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
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06/30/2005
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Title:
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CIRCUIT FOR AUTO-CLAMPING INPUT PINS TO A DEFINITE VOLTAGE DURING POWER-UP OR RESET
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