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Patent Assignment Details
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Reel/Frame:016087/0211   Pages: 8
Recorded: 04/15/2005
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
04/12/2005
Application #:
10640804
Filing Dt:
08/13/2003
Title:
INTEGRATED CIRCUIT AND ASSOCIATED DESIGN METHOD WITH ANTENNA ERROR CONTROL USING SPARE GATES
Assignors
1
Exec Dt:
07/09/2002
2
Exec Dt:
07/09/2002
3
Exec Dt:
07/09/2002
4
Exec Dt:
07/09/2002
5
Exec Dt:
07/09/2002
6
Exec Dt:
07/09/2002
Assignee
1
5555 NE MOORE CT
HILLSBORO, OREGON 97124
Correspondence name and address
LATTICE SEMICONDUCTOR CORPORATION
MARK L BECKER
5555 NE MORRE CT
HILLSBORO, OR 97124

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