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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:058298/0235   Pages: 8
Recorded: 10/25/2021
Attorney Dkt #:BSL20211025
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 58
1
Patent #:
6498509
Issue Dt:
12/24/2002
Application #:
09896817
Filing Dt:
06/29/2001
Publication #:
US20020018367
Pub Dt:
02/14/2002
Title:
DEVICE TO CONTROL THE POWER SUPPLY IN AN INTEGRATED CIRCUIT COMPRISING ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS
2
Patent #:
6973591
Issue Dt:
12/06/2005
Application #:
09981624
Filing Dt:
10/16/2001
Publication #:
US20020059542
Pub Dt:
05/16/2002
Title:
ON-CHIP EMULATOR COMMUNICATION FOR DEBUGGING
3
Patent #:
7180175
Issue Dt:
02/20/2007
Application #:
10061507
Filing Dt:
02/01/2002
Publication #:
US20030146507
Pub Dt:
08/07/2003
Title:
THERMALLY-ENHANCED BALL GRID ARRAY PACKAGE STRUCTURE AND METHOD
4
Patent #:
7096581
Issue Dt:
08/29/2006
Application #:
10091743
Filing Dt:
03/06/2002
Publication #:
US20030167632
Pub Dt:
09/11/2003
Title:
METHOD FOR PROVIDING A REDISTRIBUTION METAL LAYER IN AN INTEGRATED CIRCUIT
5
Patent #:
6885530
Issue Dt:
04/26/2005
Application #:
10166876
Filing Dt:
06/11/2002
Publication #:
US20030227729
Pub Dt:
12/11/2003
Title:
POWER LIMITING TIME DELAY CIRCUIT
6
Patent #:
6818953
Issue Dt:
11/16/2004
Application #:
10278434
Filing Dt:
10/23/2002
Publication #:
US20030076640
Pub Dt:
04/24/2003
Title:
PROTECTION OF AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES AND OTHER OVERVOLTAGES
7
Patent #:
7362204
Issue Dt:
04/22/2008
Application #:
10436961
Filing Dt:
05/13/2003
Publication #:
US20030210122
Pub Dt:
11/13/2003
Title:
INDUCTANCE WITH A MIDPOINT
8
Patent #:
7474311
Issue Dt:
01/06/2009
Application #:
10924748
Filing Dt:
08/24/2004
Publication #:
US20050078119
Pub Dt:
04/14/2005
Title:
DEVICE AND METHOD FOR PROCESSING VIDEO AND GRAPHICS DATA
9
Patent #:
7102860
Issue Dt:
09/05/2006
Application #:
11059838
Filing Dt:
02/17/2005
Publication #:
US20050140344
Pub Dt:
06/30/2005
Title:
POWER LIMITING TIME DELAY CIRCUIT
10
Patent #:
NONE
Issue Dt:
Application #:
11172515
Filing Dt:
06/30/2005
Publication #:
US20070013361
Pub Dt:
01/18/2007
Title:
SEMICONDUCTOR DEVICE HAVING AN INTEGRATED, SELF-REGULATED PWM CURRENT AND POWER LIMITER AND METHOD
11
Patent #:
7786582
Issue Dt:
08/31/2010
Application #:
11455503
Filing Dt:
06/19/2006
Publication #:
US20060234423
Pub Dt:
10/19/2006
Title:
SYSTEM FOR PROVIDING A REDISTRIBUTION METAL LAYER IN AN INTEGRATED CIRCUIT
12
Patent #:
7315079
Issue Dt:
01/01/2008
Application #:
11709928
Filing Dt:
02/20/2007
Publication #:
US20070200224
Pub Dt:
08/30/2007
Title:
THERMALLY-ENHANCED BALL GRID ARRAY PACKAGE STRUCTURE AND METHOD
13
Patent #:
7671571
Issue Dt:
03/02/2010
Application #:
12070710
Filing Dt:
02/20/2008
Publication #:
US20080284404
Pub Dt:
11/20/2008
Title:
SEMICONDUCTOR DEVICE HAVING AN INTEGRATED, SELF- REGULATED PWM CURRENT AND POWER LIMITER AND METHOD
14
Patent #:
8884422
Issue Dt:
11/11/2014
Application #:
12651365
Filing Dt:
12/31/2009
Publication #:
US20110156250
Pub Dt:
06/30/2011
Title:
FLIP-CHIP FAN-OUT WAFER LEVEL PACKAGE FOR PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE
15
Patent #:
8163645
Issue Dt:
04/24/2012
Application #:
12804870
Filing Dt:
07/30/2010
Publication #:
US20100297841
Pub Dt:
11/25/2010
Title:
METHOD FOR PROVIDING A REDISTRIBUTION METAL LAYER IN AN INTEGRATED CIRCUIT
16
Patent #:
NONE
Issue Dt:
Application #:
13454570
Filing Dt:
04/24/2012
Publication #:
US20130277747
Pub Dt:
10/24/2013
Title:
TRANSISTOR HAVING A STRESSED BODY
17
Patent #:
9012999
Issue Dt:
04/21/2015
Application #:
13590548
Filing Dt:
08/21/2012
Publication #:
US20140054715
Pub Dt:
02/27/2014
Title:
SEMICONDUCTOR DEVICE WITH AN INCLINED SOURCE/DRAIN AND ASSOCIATED METHODS
18
Patent #:
9093556
Issue Dt:
07/28/2015
Application #:
13590756
Filing Dt:
08/21/2012
Publication #:
US20140054706
Pub Dt:
02/27/2014
Title:
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
19
Patent #:
8759874
Issue Dt:
06/24/2014
Application #:
13691070
Filing Dt:
11/30/2012
Publication #:
US20140151746
Pub Dt:
06/05/2014
Title:
FINFET DEVICE WITH ISOLATED CHANNEL
20
Patent #:
10134895
Issue Dt:
11/20/2018
Application #:
13692632
Filing Dt:
12/03/2012
Publication #:
US20140151759
Pub Dt:
06/05/2014
Title:
FACET-FREE STRAINED SILICON TRANSISTOR
21
Patent #:
8956942
Issue Dt:
02/17/2015
Application #:
13725528
Filing Dt:
12/21/2012
Publication #:
US20140175554
Pub Dt:
06/26/2014
Title:
METHOD OF FORMING A FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
22
Patent #:
9219133
Issue Dt:
12/22/2015
Application #:
13905586
Filing Dt:
05/30/2013
Publication #:
US20140357040
Pub Dt:
12/04/2014
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT
23
Patent #:
NONE
Issue Dt:
Application #:
13906789
Filing Dt:
05/31/2013
Publication #:
US20140353716
Pub Dt:
12/04/2014
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
24
Patent #:
9685380
Issue Dt:
06/20/2017
Application #:
13907613
Filing Dt:
05/31/2013
Publication #:
US20140353760
Pub Dt:
12/04/2014
Title:
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
25
Patent #:
9000498
Issue Dt:
04/07/2015
Application #:
13931581
Filing Dt:
06/28/2013
Publication #:
US20150001595
Pub Dt:
01/01/2015
Title:
FINFET WITH MULTIPLE CONCENTRATION PERCENTAGES
26
Patent #:
9099559
Issue Dt:
08/04/2015
Application #:
14027758
Filing Dt:
09/16/2013
Publication #:
US20150076514
Pub Dt:
03/19/2015
Title:
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
27
Patent #:
8933737
Issue Dt:
01/13/2015
Application #:
14046041
Filing Dt:
10/04/2013
Publication #:
US20150002197
Pub Dt:
01/01/2015
Title:
SYSTEM AND METHOD FOR VARIABLE FREQUENCY CLOCK GENERATION
28
Patent #:
9136384
Issue Dt:
09/15/2015
Application #:
14097570
Filing Dt:
12/05/2013
Publication #:
US20150162434
Pub Dt:
06/11/2015
Title:
METHOD FOR THE FORMATION OF A FINFET DEVICE HAVING PARTIALLY DIELECTRIC ISOLATED FIN STRUCTURE
29
Patent #:
9660080
Issue Dt:
05/23/2017
Application #:
14194215
Filing Dt:
02/28/2014
Publication #:
US20150249153
Pub Dt:
09/03/2015
Title:
MULTI-LAYER STRAINED CHANNEL FINFET
30
Patent #:
9123809
Issue Dt:
09/01/2015
Application #:
14494979
Filing Dt:
09/24/2014
Publication #:
US20150008521
Pub Dt:
01/08/2015
Title:
TRANSISTOR HAVING A STRESSED BODY
31
Patent #:
9520393
Issue Dt:
12/13/2016
Application #:
14587872
Filing Dt:
12/31/2014
Publication #:
US20150108585
Pub Dt:
04/23/2015
Title:
FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
32
Patent #:
9419111
Issue Dt:
08/16/2016
Application #:
14748270
Filing Dt:
06/24/2015
Publication #:
US20150303285
Pub Dt:
10/22/2015
Title:
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
33
Patent #:
9548361
Issue Dt:
01/17/2017
Application #:
14755663
Filing Dt:
06/30/2015
Publication #:
US20170005169
Pub Dt:
01/05/2017
Title:
METHOD OF USING A SACRIFICIAL GATE STRUCTURE TO MAKE A METAL GATE FINFET TRANSISTOR
34
Patent #:
9406783
Issue Dt:
08/02/2016
Application #:
14788737
Filing Dt:
06/30/2015
Publication #:
US20150303282
Pub Dt:
10/22/2015
Title:
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
35
Patent #:
9385051
Issue Dt:
07/05/2016
Application #:
14822959
Filing Dt:
08/11/2015
Publication #:
US20150348851
Pub Dt:
12/03/2015
Title:
METHOD FOR THE FORMATION OF A FINFET DEVICE HAVING PARTIALLY DIELECTRIC ISOLATED FIN STRUCTURE
36
Patent #:
10205022
Issue Dt:
02/12/2019
Application #:
14939729
Filing Dt:
11/12/2015
Publication #:
US20160064566
Pub Dt:
03/03/2016
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT
37
Patent #:
9847260
Issue Dt:
12/19/2017
Application #:
14969393
Filing Dt:
12/15/2015
Publication #:
US20160111338
Pub Dt:
04/21/2016
Title:
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
38
Patent #:
9905662
Issue Dt:
02/27/2018
Application #:
14976781
Filing Dt:
12/21/2015
Publication #:
US20160104772
Pub Dt:
04/14/2016
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
39
Patent #:
10134899
Issue Dt:
11/20/2018
Application #:
14983070
Filing Dt:
12/29/2015
Publication #:
US20160149038
Pub Dt:
05/26/2016
Title:
FACET-FREE STRAINED SILICON TRANSISTOR
40
Patent #:
9660081
Issue Dt:
05/23/2017
Application #:
15084312
Filing Dt:
03/29/2016
Publication #:
US20160211376
Pub Dt:
07/21/2016
Title:
METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
41
Patent #:
10199392
Issue Dt:
02/05/2019
Application #:
15169462
Filing Dt:
05/31/2016
Publication #:
US20160276371
Pub Dt:
09/22/2016
Title:
FINFET DEVICE HAVING A PARTIALLY DIELECTRIC ISOLATED FIN STRUCTURE
42
Patent #:
10043805
Issue Dt:
08/07/2018
Application #:
15197509
Filing Dt:
06/29/2016
Publication #:
US20160307899
Pub Dt:
10/20/2016
Title:
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
43
Patent #:
10062690
Issue Dt:
08/28/2018
Application #:
15209662
Filing Dt:
07/13/2016
Publication #:
US20160322356
Pub Dt:
11/03/2016
Title:
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
44
Patent #:
9991351
Issue Dt:
06/05/2018
Application #:
15331714
Filing Dt:
10/21/2016
Publication #:
US20170040427
Pub Dt:
02/09/2017
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
45
Patent #:
9893147
Issue Dt:
02/13/2018
Application #:
15345250
Filing Dt:
11/07/2016
Publication #:
US20170053981
Pub Dt:
02/23/2017
Title:
FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
46
Patent #:
9917194
Issue Dt:
03/13/2018
Application #:
15365640
Filing Dt:
11/30/2016
Publication #:
US20170084733
Pub Dt:
03/23/2017
Title:
SELF-ALIGNED SILICON GERMANIUM FINFET WITH RELAXED CHANNEL REGION
47
Patent #:
10068908
Issue Dt:
09/04/2018
Application #:
15489360
Filing Dt:
04/17/2017
Publication #:
US20170221903
Pub Dt:
08/03/2017
Title:
METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
48
Patent #:
10340195
Issue Dt:
07/02/2019
Application #:
15813071
Filing Dt:
11/14/2017
Publication #:
US20180068902
Pub Dt:
03/08/2018
Title:
METHOD TO CO-INTEGRATE SIGE AND SI CHANNELS FOR FINFET DEVICES
49
Patent #:
10170546
Issue Dt:
01/01/2019
Application #:
15873644
Filing Dt:
01/17/2018
Publication #:
US20180145133
Pub Dt:
05/24/2018
Title:
FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
50
Patent #:
10256341
Issue Dt:
04/09/2019
Application #:
15884843
Filing Dt:
01/31/2018
Publication #:
US20180158945
Pub Dt:
06/07/2018
Title:
SELF-ALIGNED SILICON GERMANIUM FINFET WITH RELAXED CHANNEL REGION
51
Patent #:
NONE
Issue Dt:
Application #:
15979326
Filing Dt:
05/14/2018
Publication #:
US20180261674
Pub Dt:
09/13/2018
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
52
Patent #:
10515965
Issue Dt:
12/24/2019
Application #:
16035441
Filing Dt:
07/13/2018
Publication #:
US20180331106
Pub Dt:
11/15/2018
Title:
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
53
Patent #:
10580771
Issue Dt:
03/03/2020
Application #:
16049685
Filing Dt:
07/30/2018
Publication #:
US20180350808
Pub Dt:
12/06/2018
Title:
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
54
Patent #:
11670554
Issue Dt:
06/06/2023
Application #:
16426579
Filing Dt:
05/30/2019
Publication #:
US20190279912
Pub Dt:
09/12/2019
Title:
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
55
Patent #:
10854606
Issue Dt:
12/01/2020
Application #:
16697103
Filing Dt:
11/26/2019
Publication #:
US20200098760
Pub Dt:
03/26/2020
Title:
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
56
Patent #:
11069682
Issue Dt:
07/20/2021
Application #:
16751036
Filing Dt:
01/23/2020
Publication #:
US20200161299
Pub Dt:
05/21/2020
Title:
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
57
Patent #:
11587928
Issue Dt:
02/21/2023
Application #:
17093528
Filing Dt:
11/09/2020
Publication #:
US20210057414
Pub Dt:
02/25/2021
Title:
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
58
Patent #:
11610886
Issue Dt:
03/21/2023
Application #:
17365682
Filing Dt:
07/01/2021
Publication #:
US20210327874
Pub Dt:
10/21/2021
Title:
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
Assignor
1
STMICROELECTRONICS INTERNATIONAL N.V.
Exec Dt:
10/16/2021
Assignee
1
BELL SEMICONDUCTOR, LLC
ONE WEST BROAD STREET
SUITE 901
BETHLEHEM, PENNSYLVANIA 18018
Correspondence name and address
SCOTT WIDDOWSON
ONE WEST BROAD STREET
SUITE 901
BETHLEHEM, PA 18018

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