Total properties:
250
Page
3
of
3
Pages:
1 2 3 |
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
13235755
|
Filing Dt:
|
09/19/2011
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A COMPONENT IN AN ENCAPSULANT CAVITY AND METHOD OF FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13239373
|
Filing Dt:
|
09/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT SYSTEM WITH TEST PADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13268091
|
Filing Dt:
|
10/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13269442
|
Filing Dt:
|
10/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
13272034
|
Filing Dt:
|
10/12/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
13300088
|
Filing Dt:
|
11/18/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13314984
|
Filing Dt:
|
12/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13324380
|
Filing Dt:
|
12/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
04/12/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13325903
|
Filing Dt:
|
12/14/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13326090
|
Filing Dt:
|
12/14/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13326173
|
Filing Dt:
|
12/14/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13326728
|
Filing Dt:
|
12/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13326891
|
Filing Dt:
|
12/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13327091
|
Filing Dt:
|
12/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSISTANCE MOLD AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13360549
|
Filing Dt:
|
01/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS IN PERIPHERAL REGION CONNECTING SHIELDING LAYER TO GROUND
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13417034
|
Filing Dt:
|
03/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13419242
|
Filing Dt:
|
03/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13421770
|
Filing Dt:
|
03/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming With Three-Dimensional Vertically Oriented Integrated Capacitors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13423263
|
Filing Dt:
|
03/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13423739
|
Filing Dt:
|
03/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13423832
|
Filing Dt:
|
03/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13425277
|
Filing Dt:
|
03/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13426442
|
Filing Dt:
|
03/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13431816
|
Filing Dt:
|
03/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
|
Title:
|
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13438155
|
Filing Dt:
|
04/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13441691
|
Filing Dt:
|
04/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STUD BUMPS OVER EMBEDDED DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13458289
|
Filing Dt:
|
04/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13464979
|
Filing Dt:
|
05/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
|
Title:
|
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13476899
|
Filing Dt:
|
05/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13477630
|
Filing Dt:
|
05/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKABLE DEVICES AND A METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13492646
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13492765
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13523261
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TIEBAR-LESS DESIGN AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13531941
|
Filing Dt:
|
06/25/2012
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDING SPACER AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13542120
|
Filing Dt:
|
07/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13556064
|
Filing Dt:
|
07/23/2012
|
|
Title:
|
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13556106
|
Filing Dt:
|
07/23/2012
|
|
Title:
|
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13558586
|
Filing Dt:
|
07/26/2012
|
|
Title:
|
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13558953
|
Filing Dt:
|
07/26/2012
|
|
Title:
|
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13559430
|
Filing Dt:
|
07/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13606631
|
Filing Dt:
|
09/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13615308
|
Filing Dt:
|
09/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13679615
|
Filing Dt:
|
11/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13691427
|
Filing Dt:
|
11/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BUMP FORMED ON SUBSTRATE TO PREVENT EXTRIMELY-LOW DIELECTRIC CONSTANT (ELK) INTERLAYER DIELECTRIC LAYER (ILD) DELAMINATION DURING REFLOW PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
13706818
|
Filing Dt:
|
12/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13750975
|
Filing Dt:
|
01/25/2013
|
|
Title:
|
METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13752157
|
Filing Dt:
|
01/28/2013
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13756679
|
Filing Dt:
|
02/01/2013
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13756779
|
Filing Dt:
|
02/01/2013
|
|
Title:
|
Bump-On-Lead Flip Chip Interconnection
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13756905
|
Filing Dt:
|
02/01/2013
|
|
Title:
|
SOLDER JOINT FLIP CHIP INTERCONNECTION
|
|
