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Reel/Frame:014799/0240   Pages: 4
Recorded: 12/15/2003
Conveyance: SECURITY AGREEMENT
Total properties: 12
1
Patent #:
Issue Dt:
06/03/2003
Application #:
09712418
Filing Dt:
11/13/2000
Title:
METHOD AND SYSTEM FOR AUTOMATICALLY GENERATING LOW LEVEL PROGRAM COMMANDS AS DEPENDENCY GRAPHS FROM HIGH LEVEL PHYSICAL DESIGN STAGES
2
Patent #:
Issue Dt:
04/29/2003
Application #:
09714296
Filing Dt:
11/15/2000
Title:
METHOD AND SYSTEM FOR IMPLEMENTING A USER INTERFACE FOR PERFORMING PHYSICAL DESIGN OPERATIONS ON AN INTEGRATED CIRCUIT NETLIST
3
Patent #:
Issue Dt:
02/15/2005
Application #:
09714722
Filing Dt:
11/15/2000
Title:
OPTIMIZATION OF ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN
4
Patent #:
Issue Dt:
04/22/2003
Application #:
09908957
Filing Dt:
07/18/2001
Title:
METHOD AND SYSTEM FOR IMPLEMENTING A GRAPHICAL USER INTERFACE FOR DEPICTING LOOSE FLY LINE INTERCONNECTIONS BETWEEN MULTIPLE BLOCKS OF AN INTEGRATED CIRCUIT NETLIST
5
Patent #:
Issue Dt:
05/13/2003
Application #:
09909050
Filing Dt:
07/18/2001
Title:
METHOD AND SYSTEM FOR IMPLEMENTING A GRAPHICAL USER INTERFACE FOR DEFINING AND LINKING MULTIPLE ATTACH POINTS FOR MULTIPLE BLOCKS OF AN INTEGRATED CIRCUIT NETLIST
6
Patent #:
Issue Dt:
05/13/2003
Application #:
09909354
Filing Dt:
07/18/2001
Title:
METHOD AND SYSTEM FOR MAINTAINING ELEMENT ABSTRACTS OF AN INTEGRATED CIRCUIT NETLIST USING A MASTER LIBRARY FILE AND MODIFIABLE MASTER LIBRARY FILE
7
Patent #:
Issue Dt:
06/29/2004
Application #:
10104786
Filing Dt:
03/22/2002
Title:
FACILITATING VERIFICATION IN ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN
8
Patent #:
Issue Dt:
02/08/2005
Application #:
10104813
Filing Dt:
03/22/2002
Title:
FACILITATING PRESS OPERATION IN ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN
9
Patent #:
Issue Dt:
03/08/2005
Application #:
10104960
Filing Dt:
03/22/2002
Title:
OPTIMIZATION OF THE TOP LEVEL IN ABUTTED-PIN HEIRARCHICAL PHYSICAL DESIGN
10
Patent #:
Issue Dt:
05/11/2004
Application #:
10264679
Filing Dt:
10/03/2002
Title:
METHOD OF CUSTOMIZING AND USING MAPS IN GENERATING THE PADRING LAYOUT DESIGN
11
Patent #:
Issue Dt:
11/23/2004
Application #:
10264680
Filing Dt:
10/03/2002
Title:
METHOD OF GENERATING THE PADRING LAYOUT DESIGN USING AUTOMATION
12
Patent #:
Issue Dt:
10/03/2006
Application #:
10264691
Filing Dt:
10/03/2002
Title:
METHOD OF OPTIMIZING PLACEMENT AND ROUTING OF EDGE LOGIC IN PADRING LAYOUT DESIGN
Assignor
1
Exec Dt:
10/23/2003
Assignee
1
3003 TASMAN DR.
LOAN DOCUMENTATION HA155
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
SILICON VALLEY BANK
MARIBEL ARTEAGA
LOAN DOCUMENTATION HA155
3003 TASMAN DR.
SANTA CLARA, CA 95054

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