Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024010/0241 | |
| Pages: | 18 |
| | Recorded: | 03/02/2010 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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12/11/2012
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Application #:
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12139010
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Filing Dt:
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06/13/2008
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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INP-BASED TRANSISTOR FABRICATION
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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12495161
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Filing Dt:
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06/30/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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REDUCTION OF EDGE EFFECTS FROM ASPECT RATIO TRAPPING
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Patent #:
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Issue Dt:
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03/17/2015
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Application #:
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12503597
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Filing Dt:
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07/15/2009
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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POLISHING OF SMALL COMPOSITE SEMICONDUCTOR MATERIALS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12562206
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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03/25/2010
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Title:
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FABRICATION AND STRUCTURES OF CRYSTALLINE MATERIAL
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Patent #:
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Issue Dt:
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08/28/2012
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Application #:
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12565863
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Filing Dt:
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09/24/2009
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Publication #:
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Pub Dt:
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04/01/2010
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Title:
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SEMICONDUCTOR SENSOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES
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Patent #:
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Issue Dt:
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12/22/2015
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Application #:
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12573589
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Filing Dt:
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10/05/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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METHOD OF FABRICATING CMOS INVERTER AND INTEGRATED CIRCUITS UTILIZING STRAINED SILICON SURFACE CHANNEL MOSFETS
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Assignee
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| NO. 8, LI-HSIN RD. 6 |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 |
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Correspondence name and address
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SLATER & MATSIL, L.L.P.
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17950 PRESTON ROAD, SUITE 1000
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DALLAS, TX 75252
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