Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 040417/0248 | |
| Pages: | 7 |
| | Recorded: | 10/19/2016 | | |
Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 017205 FRAME: 0248. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. |
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Total properties:
4
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10004976
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Filing Dt:
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12/03/2001
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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INTEGRATED CIRCUITS WITH SCALABLE DESIGN
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10024943
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Filing Dt:
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12/18/2001
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Publication #:
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Pub Dt:
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06/19/2003
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Title:
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DYNAMIC MATCHING IN CASCODE CIRCUITS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10025437
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Filing Dt:
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12/18/2001
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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Internal impedance match in integrated circuits
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10327512
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Filing Dt:
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12/19/2002
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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COMPACT LAYOUT FOR A SEMICONDUCTOR DEVICE
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Assignee
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131 MOUNT BETHEL ROAD |
WARREN, NEW JERSEY 07059 |
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Correspondence name and address
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KELLEY DRYE & WARREN LLP
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ONE JEFFERSON ROAD
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PARSIPPANY, NJ 07054
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