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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	007854/0249			Pages:	34
		Recorded:	03/19/1996
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 10

Patent #:	5048690	Issue Dt:	09/17/1991	Application #:	07400411	Filing Dt:	08/30/1989
Title:	CARTON AND BLANK FOR MAKING SAME

Patent #:	5280474	Issue Dt:	01/18/1994	Application #:	07461492	Filing Dt:	01/05/1990
Title:	SCALABLE PROCESSOR TO PROCESSOR AND PROCESSOR- TO -I/O INTERCONNECTION NETWORK AND METHOD FOR PARALLEL PROCESSING ARRAYS

Patent #:	5313590	Issue Dt:	05/17/1994	Application #:	07461572	Filing Dt:	01/05/1990
Title:	SYSTEM HAVING FIXEDLY PRIORIZED AND GROUPED BY POSITIONS I/O LINES FOR INTERCONNECTING ROUTER ELEMENTS IN PLURALITY OF STAGES WITHIN PARRA- LLEL COMPUTER

Patent #:	5345556	Issue Dt:	09/06/1994	Application #:	07693846	Filing Dt:	04/30/1991
Title:	ROUTER CHIP WITH QUAD-CROSSBAR AND HYPERBAR PERSONALITIES

Patent #:	5450330	Issue Dt:	09/12/1995	Application #:	07693850	Filing Dt:	04/30/1991
Title:	DIAGNOSTIC CIRCUITRY

Patent #:	5243699	Issue Dt:	09/07/1993	Application #:	07802944	Filing Dt:	12/06/1991
Title:	INPUT/OUTPUT SYSTEM FOR PARALLEL PROCESSING ARRAYS

Patent #:	5488694	Issue Dt:	01/30/1996	Application #:	07937639	Filing Dt:	08/28/1992
Title:	BROADCASTING HEADERS TO CONFIGURE PHYSICAL DEVICES INTERFACING A DATA BUS WITH A LOGICAL ASSIGNMENT AND TO EFFECT BLOCK DATA TRANSFERS BETWEEN THE CONFIGURED LOGICAL DEVICES

Patent #:	5542074	Issue Dt:	07/30/1996	Application #:	07965938	Filing Dt:	10/22/1992
Title:	PARALLEL PROCESSOR SYSTEM WITH HIGHLY FLEXIBLE LOCAL CONTROL CAPABILITY, INCLUDING SELECTIVE INVERSION OF INSTRUCTION SIGNAL AND CONTROL OF BIT SHIFT AMOUNT

Patent #:	5434977	Issue Dt:	07/18/1995	Application #:	08170657	Filing Dt:	12/20/1993
Title:	ROUTER CHIP FOR PROCESSING ROUTING ADDRESS BITS AND PROTOCOL BITS USING SAME CIRCUITRY

Patent #:	5598408	Issue Dt:	01/28/1997	Application #:	08182250	Filing Dt:	01/14/1994
Title:	SCALABLE PROCESSOR-TO PROCESSOR TO AND PROCESSOR-TO I/O INTERCONNECTION NETWORK AND METHOD FOR PARALLEL PROCESSING ARRAYS

Assignor

Exec Dt:

08/23/1995

Assignee

2750 SAND HILL ROAD

MENLO PARK, CALIFORNIA 94025

Correspondence name and address
	BROBECK, PHLEGER & HARRISON
	MARY R. HOETS
	ONE MARKET PLAZA
	SPEAR STREET TOWER
	SAN FRANCISCO, CALIFORNIA 94105

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