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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09822783
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Filing Dt:
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03/30/2001
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Title:
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MECHANISM FOR EXTENDING PROPERTIES OF VIRTUAL MEMORY PAGES BY A TLB
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09905180
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Filing Dt:
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07/13/2001
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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MECHANISM FOR PROGRAMMABLE MODIFICATION OF MEMORY MAPPING GRANULARITY
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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09921377
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Filing Dt:
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08/02/2001
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Title:
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READ-ONLY ACCESS TO CPO REGISTERS
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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09921400
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Filing Dt:
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08/02/2001
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Title:
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ATOMIC UPDATE OF CPO STATE
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Patent #:
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Issue Dt:
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06/23/2009
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Application #:
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09977089
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Filing Dt:
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10/12/2001
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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CONFIGURABLE PRIORITIZATION OF CORE GENERATED INTERRUPTS
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10238993
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Filing Dt:
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09/06/2002
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Publication #:
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Pub Dt:
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03/11/2004
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Title:
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METHOD AND APPARATUS FOR CLEARING HAZARDS USING JUMP INSTRUCTIONS
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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10279210
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Filing Dt:
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10/22/2002
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Title:
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INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10468434
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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ADJUSTING THREAD INSTRUCTION ISSUE RATE BASED ON DEVIATION OF ACTUAL EXECUTED NUMBER FROM INTENDED RATE CUMULATIVE NUMBER
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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10684350
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
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03/03/2005
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Title:
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MECHANISMS FOR ASSURING QUALITY OF SERVICE FOR PROGRAMS EXECUTING ON A MULTITHREADED PROCESSOR
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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10783960
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Filing Dt:
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02/20/2004
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Title:
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METHOD AND APPARATUS FOR GLOBAL ORDERING TO INSURE LATENCY INDEPENDENT COHERENCE
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Patent #:
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Issue Dt:
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10/27/2009
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Application #:
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10928746
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
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06/02/2005
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Title:
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APPARATUS, METHOD, AND INSTRUCTION FOR INITIATION OF CONCURRENT INSTRUCTION STREAMS IN A MULTITHREADING MICROPROCESSOR
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Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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10929097
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
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10/27/2005
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Title:
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APPARATUS, METHOD, AND INSTRUCTION FOR SOFTWARE MANAGEMENT OF MULTIPLE COMPUTATIONAL CONTEXTS IN A MULTITHREADED MICROPROCESSOR
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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10929102
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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MECHANISMS FOR DYNAMIC CONFIGURATION OF VIRTUAL PROCESSOR RESOURCES
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Patent #:
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Issue Dt:
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01/22/2008
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Application #:
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10929342
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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INTEGRATED MECHANISM FOR SUSPENSION AND DEALLOCATION OF COMPUTATIONAL THREADS OF EXECUTION IN A PROCESSOR
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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10949958
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Filing Dt:
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09/24/2004
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Publication #:
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Pub Dt:
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10/20/2005
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Title:
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METHOD AND APPARATUS FOR DYNAMIC ALLOCATION OF RESOURCES TO EXECUTING THREADS IN A MULTI-THREADED PROCESSOR
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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10954988
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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08/09/2007
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Title:
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SYNCHRONIZED STORAGE PROVIDING MULTIPLE SYNCHRONIZATION SEMANTICS
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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10955231
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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11/10/2005
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Title:
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SMART MEMORY BASED SYNCHRONIZATION CONTROLLER FOR A MULTI-THREADED MULTIPROCESSOR SOC
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Patent #:
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Issue Dt:
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12/14/2010
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Application #:
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11051978
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Filing Dt:
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02/04/2005
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Publication #:
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Pub Dt:
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08/10/2006
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Title:
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INSTRUCTION/SKID BUFFERS IN A MULTITHREADING MICROPROCESSOR THAT STORE DISPATCHED INSTRUCTIONS TO AVOID RE-FETCHING FLUSHED INSTRUCTIONS
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Patent #:
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Issue Dt:
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02/02/2010
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Application #:
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11051979
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Filing Dt:
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02/04/2005
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Publication #:
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Pub Dt:
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08/10/2006
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Title:
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MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11051997
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Filing Dt:
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02/04/2005
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Publication #:
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Pub Dt:
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08/10/2006
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Title:
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INTERFACING EXTERNAL THREAD PRIORITIZING POLICY ENFORCING LOGIC WITH CUSTOMER MODIFIABLE REGISTER TO PROCESSOR INTERNAL SCHEDULER
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Patent #:
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Issue Dt:
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07/07/2009
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Application #:
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11075041
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Filing Dt:
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03/08/2005
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Publication #:
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Pub Dt:
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09/14/2006
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Title:
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THREE-TIERED TRANSLATION LOOKASIDE BUFFER HIERARCHY IN A MULTITHREADING MICROPROCESSOR
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Patent #:
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Issue Dt:
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05/01/2012
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11284069
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11/21/2005
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Pub Dt:
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05/11/2006
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Title:
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METHOD AND APPARATUS FOR CLEARING HAZARDS USING JUMP INSTRUCTIONS
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Patent #:
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12/07/2010
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11313272
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12/20/2005
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Pub Dt:
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07/20/2006
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Title:
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SOFTWARE EMULATION OF DIRECTED EXCEPTIONS IN A MULTITHREADING PROCESSOR
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Patent #:
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05/12/2015
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11313296
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12/20/2005
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Pub Dt:
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07/20/2006
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Title:
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PREEMPTIVE MULTITASKING EMPLOYING SOFTWARE EMULATION OF DIRECTED EXCEPTIONS IN A MULTITHREADING PROCESSOR
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Patent #:
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08/26/2008
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11330914
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01/11/2006
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02/22/2007
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Title:
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SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
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11/16/2010
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11330915
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01/11/2006
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Pub Dt:
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02/22/2007
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Title:
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SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
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01/11/2011
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11330916
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01/11/2006
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02/22/2007
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Title:
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SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
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06/23/2015
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11388484
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03/23/2006
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Title:
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02/26/2008
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11524822
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09/21/2006
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01/18/2007
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10/06/2009
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11567290
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12/06/2006
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10/04/2007
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05/25/2010
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11615960
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12/23/2006
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05/10/2007
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SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
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05/25/2010
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11615963
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12/23/2006
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05/10/2007
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SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
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06/01/2010
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11615964
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12/23/2006
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05/10/2007
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SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
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03/09/2010
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11615965
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12/23/2006
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05/10/2007
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Title:
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SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS
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09/22/2009
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11632567
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01/11/2008
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10/09/2008
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MICROPROCESSOR OUTPUT PORTS AND CONTROL OF INSTRUCTIONS PROVIDED THEREFROM
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08/10/2010
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11681610
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03/02/2007
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04/17/2008
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HORIZONTALLY-SHARED CACHE VICTIMS IN MULTIPLE CORE PROCESSORS
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10/08/2019
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11704725
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02/09/2007
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08/30/2007
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06/26/2012
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03/20/2007
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12/13/2007
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EXPANDED FUNCTIONALITY OF PROCESSOR OPERATIONS WITHIN A FIXED WIDTH INSTRUCTION ENCODING
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06/15/2010
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11767247
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06/22/2007
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12/25/2008
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03/09/2010
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12/03/2007
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06/12/2008
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SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONDITIONALLY SUSPENDING ISSUING INSTRUCTIONS OF A THREAD
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05/24/2016
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12322942
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02/09/2009
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08/20/2009
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Prioritising of instruction fetching in microprocessor systems
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10/15/2013
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12383118
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03/19/2009
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10/01/2009
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Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
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07/08/2014
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12387152
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04/28/2009
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11/19/2009
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04/12/2011
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06/30/2009
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12/31/2009
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THREE-TIERED TRANSLATION LOOKASIDE BUFFER HIERARCHY IN A MULTITHREADING MICROPROCESSOR
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10/11/2011
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12557421
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09/10/2009
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01/07/2010
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METHOD AND APPARATUS FOR GLOBAL ORDERING TO INSURE LATENCY INDEPENDENT COHERENCE
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05/29/2012
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12576942
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10/09/2009
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02/04/2010
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INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR
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11/17/2015
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12584759
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09/11/2009
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10/28/2010
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Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
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07/31/2012
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12586649
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09/25/2009
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10/07/2010
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METHOD AND APPARATUS FOR ENSURING DATA CACHE COHERENCY
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03/27/2012
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12605201
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10/23/2009
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05/06/2010
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Title:
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APPARATUS, METHOD AND INSTRUCTION FOR INITIATION OF CONCURRENT INSTRUCTION STREAMS IN A MULTITHREADING MICROPROCESSOR
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04/03/2012
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12684564
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01/08/2010
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05/06/2010
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Title:
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MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY
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05/13/2014
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12828056
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06/30/2010
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03/03/2011
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Title:
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HORIZONTALLY-SHARED CACHE VICTIMS IN MULTIPLE CORE PROCESSORS
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08/07/2012
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12891503
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09/27/2010
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03/29/2012
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MICROPROCESSOR WITH DUAL-LEVEL ADDRESS TRANSLATION
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07/22/2014
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12891530
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09/27/2010
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03/29/2012
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