Total properties:
444
Page
3
of
5
Pages:
1 2 3 4 5
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15684081
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
Transistors and Methods of Forming Transistors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2020
|
Application #:
|
15684577
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SEMICONDUCTOR DIES SUPPORTING MULTIPLE PACKAGING CONFIGURATIONS AND ASSOCIATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
15684612
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2018
| | | | |
|
Title:
|
Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2018
|
Application #:
|
15684703
|
Filing Dt:
|
08/23/2017
|
|
Title:
|
METHODS AND SYSTEMS FOR IMPROVING POWER DELIVERY AND SIGNALING IN STACKED SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15684722
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
15684728
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
15684734
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
APPARATUSES WITH AN EMBEDDED COMBINATION LOGIC CIRCUIT FOR HIGH SPEED OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15684756
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR TESTING A SEMICONDUCTOR MEMORY DEVICE HAVING A REFERENCE MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2019
|
Application #:
|
15684763
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
MEMORY REFRESH METHODS AND APPARATUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2021
|
Application #:
|
15684773
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
MEMORY WITH VIRTUAL PAGE SIZE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15684784
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
APPARATUSES, MEMORIES, AND METHODS FOR ADDRESS DECODING AND SELECTING AN ACCESS LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
15684792
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
ON DEMAND MEMORY PAGE SIZE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2019
|
Application #:
|
15684831
|
Filing Dt:
|
08/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
MEMORY DEVICE WITH A MULTI-MODE COMMUNICATION MECHANISM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15685387
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
Fuse Element Assemblies
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2018
|
Application #:
|
15685643
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2022
|
Application #:
|
15685690
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES COMPRISING CARBON-DOPED SILICON NITRIDE AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2018
|
Application #:
|
15685855
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15685871
|
Filing Dt:
|
08/24/2017
|
|
Title:
|
SEMICONDUCTOR PITCH PATTERNING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2019
|
Application #:
|
15685878
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
15685907
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2019
|
Application #:
|
15685909
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
MEMORY READ APPARATUS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2018
|
Application #:
|
15685921
|
Filing Dt:
|
08/24/2017
|
|
Title:
|
THRUMOLD POST PACKAGE WITH REVERSE BUILD UP HYBRID ADDITIVE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15685926
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
MULTI-PARTITIONING OF MEMORIES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15685940
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15685950
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
METHODS AND SYSTEMS FOR AUTONOMOUS MEMORY SEARCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2019
|
Application #:
|
15685997
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE STRUCTURES FOR BURN-IN TESTING AND METHODS THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2019
|
Application #:
|
15686008
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SOLDER REMOVAL FROM SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
15686024
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15686029
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
15686082
|
Filing Dt:
|
08/24/2017
|
|
Title:
|
Arrays of Cross-Point Memory Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2018
|
Application #:
|
15686101
|
Filing Dt:
|
08/24/2017
|
|
Title:
|
Integrated Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2019
|
Application #:
|
15686107
|
Filing Dt:
|
08/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
Integrated Structures and Methods of Forming Integrated Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2019
|
Application #:
|
15686308
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
PHASE CHANGE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
15686389
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
CELL PILLAR STRUCTURES AND INTEGRATED FLOWS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
15686416
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2019
|
Application #:
|
15686510
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
METHODS OF PROGRAMMING MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2020
|
Application #:
|
15686526
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
VAPOR-ETCH CYCLIC PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15686754
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2020
|
Application #:
|
15686963
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
METHODS AND SYSTEMS FOR INHIBITING BONDING MATERIALS FROM CONTAMINATING A SEMICONDUCTOR PROCESSING TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2018
|
Application #:
|
15686996
|
Filing Dt:
|
08/25/2017
|
|
Title:
|
MITIGATING LINE-TO-LINE CAPACITIVE COUPLING IN A MEMORY DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
15687015
|
Filing Dt:
|
08/25/2017
|
|
Title:
|
COLD FLUID SEMICONDUCTOR DEVICE RELEASE DURING PICK AND PLACE OPERATIONS, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
15687019
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SELF-REFERENCING MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15687038
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SELF-SELECTING MEMORY CELL WITH DIELECTRIC BARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2021
|
Application #:
|
15687069
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
METHODS OF MEMORY ADDRESS VERIFICATION AND MEMORY DEVICES EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2019
|
Application #:
|
15687169
|
Filing Dt:
|
08/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
METHODS OF MEMORY ADDRESS VERIFICATION AND MEMORY DEVICES EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
15687499
|
Filing Dt:
|
08/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
METHODS OF FORMING ELECTROMAGNETIC RADIATION CONDUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2018
|
Application #:
|
15687504
|
Filing Dt:
|
08/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
Electromagnetic Radiation Emitters and Conduit Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2019
|
Application #:
|
15687506
|
Filing Dt:
|
08/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
FLUORIMETRY SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15687509
|
Filing Dt:
|
08/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
Methods of Forming Nanofluidic Channels
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2019
|
Application #:
|
15687581
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
ERASING MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2020
|
Application #:
|
15687636
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2019
|
Application #:
|
15687691
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PILLARS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2018
|
Application #:
|
15687710
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2017
| | | | |
|
Title:
|
PROGRAMMING MEMORIES WITH STEPPED PROGRAMMING PULSES INCLUDING INHIBITING A MEMORY CELL FOR A PORTION OF A PROGRAMMING PULSE AND ENABLING THAT MEMORY CELL FOR ANOTHER PORTION OF THAT PROGRAMMING PULSE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15687732
|
Filing Dt:
|
08/28/2017
|
|
Title:
|
APPARATUS CONTAINING CIRCUIT-PROTECTION DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2018
|
Application #:
|
15687813
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR CONVERTING A MASK TO AN INDEX
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
15687830
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES INCLUDING CAPACITORS, RELATED ELECTRONIC SYSTEMS, AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2020
|
Application #:
|
15688027
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2019
|
Application #:
|
15688260
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15688308
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE INCLUDING A CONTROLLER ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2018
|
Application #:
|
15688348
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
DIVISION OPERATIONS IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2018
|
Application #:
|
15688545
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2020
|
Application #:
|
15688645
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
MEMORY ARRAY RESET READ OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2021
|
Application #:
|
15688667
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
APPARATUS AND METHODS TO PERFORM READ-WHILE WRITE (RWW) OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
15688680
|
Filing Dt:
|
08/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2018
| | | | |
|
Title:
|
DYNAMIC ADJUSTMENT OF MEMORY CELL DIGIT LINE CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2019
|
Application #:
|
15688945
|
Filing Dt:
|
08/29/2017
|
|
Title:
|
REFRESH IN NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2020
|
Application #:
|
15689017
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
DECODE CIRCUITRY COUPLED TO A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2019
|
Application #:
|
15689114
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
STRIPE MAPPING IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2019
|
Application #:
|
15689155
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
THREE DIMENSIONAL MEMORY ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2018
|
Application #:
|
15689211
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2018
| | | | |
|
Title:
|
FERROELECTRIC MEMORY CELL APPARATUSES AND METHODS OF OPERATING FERROELECTRIC MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2019
|
Application #:
|
15689256
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2018
| | | | |
|
Title:
|
CROSS-POINT MEMORY AND METHODS FOR FORMING OF THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15689453
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
SCALABLE, PARAMETERIZABLE, AND SCRIPT-GENERATABLE BUFFER MANAGER ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2019
|
Application #:
|
15689459
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
METHODS OF OPERATING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2019
|
Application #:
|
15689626
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
DATA DEDUPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15689721
|
Filing Dt:
|
08/29/2017
|
|
Title:
|
CHARACTERIZATION OF DECISION FEEDBACK EQUALIZER TAPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2022
|
Application #:
|
15689735
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
CAPACITORS HAVING VERTICAL CONTACTS EXTENDING THROUGH CONDUCTIVE TIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15689747
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
READ VOLTAGE CALIBRATION BASED ON HOST IO OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
15689922
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
|
Title:
|
COMPENSATION FOR THRESHOLD VOLTAGE VARIATION OF MEMORY CELL COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2018
|
Application #:
|
15689940
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
|
Title:
|
REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
15689955
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CELLS VIA INTERPOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15689989
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
REFLOW PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15690013
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES WITH MAGNETIC AND ATTRACTER MATERIALS AND METHODS OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2020
|
Application #:
|
15690081
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2018
| | | | |
|
Title:
|
SOLID STATE TRANSDUCER DEVICES WITH SEPARATELY CONTROLLED REGIONS, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2018
|
Application #:
|
15690085
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR TIMING DOMAIN CROSSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15690200
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the First Pitch, and Methods of Forming Integrated Assemblies
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
15690209
|
Filing Dt:
|
08/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the First Pitch, and Methods of Forming Integrated Assemblies
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15690320
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
MEMORY DEVICES HAVING DISTRIBUTED CONTROLLER SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2018
|
Application #:
|
15690359
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
MEMORY AS A PROGRAMMABLE LOGIC DEVICE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15690442
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
CACHE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2019
|
Application #:
|
15690497
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/22/2018
| | | | |
|
Title:
|
SEGMENTED MEMORY AND OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2021
|
Application #:
|
15690503
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
CACHE LINE DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2019
|
Application #:
|
15690708
|
Filing Dt:
|
08/30/2017
|
|
Title:
|
INCREASED NAND PERFORMANCE UNDER HIGH THERMAL CONDITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
15690744
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
MEMORY PROGRAMMING METHODS AND MEMORY SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2019
|
Application #:
|
15690800
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
METHODS OF OPERATING A MEMORY SYSTEM INCLUDING DATA COLLECTION AND COMPRESSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2018
|
Application #:
|
15690862
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
BOOSTING CHANNELS OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2020
|
Application #:
|
15690869
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
SLC CACHE MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
15690873
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
FERROELECTRIC MEMORY CELL SENSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2021
|
Application #:
|
15690889
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
LOG DATA STORAGE FOR FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2018
|
Application #:
|
15690895
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
|
Title:
|
ACTIVE BOUNDARY QUILT ARCHITECTURE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15690903
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
FLASH MEMORY BLOCK RETIREMENT POLICY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2019
|
Application #:
|
15690920
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
NAND TEMPERATURE DATA MANAGEMENT
|
|
