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Patent Assignment Details
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Reel/Frame:006929/0259   Pages: 3
Recorded: 03/15/1994
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
08/08/1995
Application #:
08213630
Filing Dt:
03/15/1994
Title:
METHOD OF MAKING TRULY COMPLEMENTARY AND SELF-ALIGNED BIPOLAR AND CMOS TRANSISTOR STRUCTURES WITH MINIMIZED BASE AND GATE RESISTANCES AND PARASITIC CAPACITANCE
Assignors
1
Exec Dt:
03/11/1994
2
Exec Dt:
03/11/1994
3
Exec Dt:
03/11/1994
Assignee
1
2900 SEMICONDUCTOR DRIVE
SANTA CLARA, CALIFORNIA 95052-8090
Correspondence name and address
SHRINATH MALUR
LIMBACH & LIMBACH
2001 FERRY BUILDING
SAN FRANCISCO, CA 94111

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