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Patent Assignment Details
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Reel/Frame:037387/0264   Pages: 17
Recorded: 12/30/2015
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 11
1
Patent #:
Issue Dt:
12/27/2005
Application #:
10065340
Filing Dt:
10/06/2002
Title:
HARDWARE ENFORCED VIRTUAL SEQUENTIALITY
2
Patent #:
Issue Dt:
09/12/2006
Application #:
11306375
Filing Dt:
12/26/2005
Title:
PACKET PROCESSOR MEMORY INTERFACE
3
Patent #:
Issue Dt:
10/21/2008
Application #:
11530895
Filing Dt:
09/11/2006
Title:
PACKET PROCESSOR MEMORY CONFLICT PREDICTION
4
Patent #:
Issue Dt:
03/17/2009
Application #:
11930202
Filing Dt:
10/31/2007
Title:
PACKET PROCESSOR MEMORY INTERFACE WITH SPECULATIVE MEMORY READS
5
Patent #:
Issue Dt:
02/03/2009
Application #:
11930203
Filing Dt:
10/31/2007
Title:
PACKET PROCESSOR MEMORY INTERFACE WITH ACTIVE PACKET LIST
6
Patent #:
Issue Dt:
02/24/2009
Application #:
11930205
Filing Dt:
10/31/2007
Title:
PACKET PROCESSOR MEMORY INTERFACE WITH LATE ORDER BINDING
7
Patent #:
Issue Dt:
01/06/2009
Application #:
11930207
Filing Dt:
10/31/2007
Title:
PACKET PROCESSOR MEMORY INTERFACE WITH WRITE DEPENDENCY LIST
8
Patent #:
Issue Dt:
01/06/2009
Application #:
11930209
Filing Dt:
10/31/2007
Title:
PACKET PROCESSOR MEMORY INTERFACE WITH CONDITIONAL DELAYED RESTART
9
Patent #:
Issue Dt:
01/13/2009
Application #:
11930211
Filing Dt:
10/31/2007
Title:
PACKET PROCESSOR MEMORY INTERFACE WITH CONFLICT DETECTION AND CHECKPOINT REPAIR
10
Patent #:
Issue Dt:
10/28/2008
Application #:
11930214
Filing Dt:
10/31/2007
Title:
PACKET PROCESSOR MEMORY INTERFACE WITH MEMORY CONFLICT VALUE CHECKING
11
Patent #:
Issue Dt:
06/15/2010
Application #:
12400437
Filing Dt:
03/09/2009
Publication #:
Pub Dt:
07/30/2009
Title:
METHOD AND APPARATUS FOR HARDWARE ENFORCED VIRTUAL SEQUENTIALITY
Assignor
1
Exec Dt:
08/12/2015
Assignee
1
2711 CENTERVILLE RD
SUITE 400
WILMINGTON, DELAWARE 19808
Correspondence name and address
FOLEY & LARDNER
150 EAST GILMAN STREET ROAD
VEREX PLAZA
MADISON, WI 53703

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