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Reel/Frame:031591/0266   Pages: 372
Recorded: 11/06/2013
Attorney Dkt #:CRS1-39000
Conveyance: SECURITY AGREEMENT
Total properties: 6045
Page 22 of 61
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
1
Patent #:
Issue Dt:
11/28/2006
Application #:
10871402
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
12/22/2005
Title:
METHOD OF FORMING A TRANSISTOR WITH A BOTTOM GATE
2
Patent #:
Issue Dt:
03/28/2006
Application #:
10871772
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
12/22/2005
Title:
TRANSISTOR WITH VERTICAL DIELECTRIC STRUCTURE
3
Patent #:
Issue Dt:
10/16/2007
Application #:
10872057
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
12/22/2005
Title:
REFLECTIVE MASK USEFUL FOR TRANSFERRING A PATTERN USING EXTREME ULTRA VIOLET (EUV) RADIATION AND METHOD OF MAKING THE SAME
4
Patent #:
Issue Dt:
08/21/2007
Application #:
10872066
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
12/30/2004
Title:
ARRANGEMENT AND METHOD FOR DIGITAL DELAY LINE
5
Patent #:
Issue Dt:
05/06/2008
Application #:
10872077
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
03/31/2005
Title:
ARRANGEMENT AND METHOD FOR ITERATIVE DECODING
6
Patent #:
Issue Dt:
04/15/2008
Application #:
10873422
Filing Dt:
06/23/2004
Publication #:
Pub Dt:
02/17/2005
Title:
SYSTEM AND METHOD FOR LOW POWER CLEAR CHANNEL ASSESSMENT
7
Patent #:
Issue Dt:
11/28/2006
Application #:
10875105
Filing Dt:
06/23/2004
Publication #:
Pub Dt:
12/29/2005
Title:
LDMOS TRANSISTOR
8
Patent #:
Issue Dt:
08/15/2006
Application #:
10876805
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
12/29/2005
Title:
METHOD OF FORMING A NANOCLUSTER CHARGE STORAGE DEVICE
9
Patent #:
Issue Dt:
08/15/2006
Application #:
10876820
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
08/31/2006
Title:
METHOD OF FORMING A NANOCLUSTER CHARGE STORAGE DEVICE
10
Patent #:
Issue Dt:
07/07/2009
Application #:
10878839
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
12/29/2005
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH REDUCED SPACING
11
Patent #:
Issue Dt:
03/01/2005
Application #:
10878956
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
11/25/2004
Title:
VARIABLE REFRESH CONTROL FOR A MEMORY
12
Patent #:
Issue Dt:
07/11/2006
Application #:
10879242
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
12/29/2005
Title:
LEAD SOLDER INDICATOR AND METHOD
13
Patent #:
Issue Dt:
07/05/2005
Application #:
10879440
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
12/09/2004
Title:
ARTICLE COMPRISING AN OXIDE LAYER ON A GAAS-BASED SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING SAME
14
Patent #:
Issue Dt:
06/15/2010
Application #:
10879991
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD AND APPARATUS FOR SELECTIVELY OPTIMIZING INTERPRETED LANGUAGE CODE
15
Patent #:
Issue Dt:
10/31/2006
Application #:
10880681
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
SCRIBE STREET STRUCTURE FOR BACKEND INTERCONNECT SEMICONDUCTOR WAFER INTEGRATION
16
Patent #:
Issue Dt:
01/02/2007
Application #:
10880685
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A STRAINED SEMICONDUCTOR LAYER
17
Patent #:
Issue Dt:
03/24/2009
Application #:
10881144
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
ULTRA-THIN DIE AND METHOD OF FABRICATING SAME
18
Patent #:
Issue Dt:
04/08/2008
Application #:
10881678
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
SCHOTTKY DEVICE AND METHOD OF FORMING
19
Patent #:
Issue Dt:
04/10/2007
Application #:
10882482
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD OF PASSIVATING OXIDE/COMPOUND SEMICONDUCTOR INTERFACE
20
Patent #:
Issue Dt:
11/28/2006
Application #:
10883180
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES COMPRISING HAFNIUM OXIDE MODIFIED WITH LANTHANUM, A LANTHANIDE-SERIES METAL, OR A COMBINATION THEREOF
21
Patent #:
Issue Dt:
02/08/2005
Application #:
10883181
Filing Dt:
06/30/2004
Title:
METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES COMPRISING EPITAXIAL HF3SI2 LAYERS
22
Patent #:
Issue Dt:
11/01/2005
Application #:
10883182
Filing Dt:
06/30/2004
Title:
METHOD OF FABRICATING THREE DIMENSIONAL GATE STRUCTURE USING OXYGEN DIFFUSION
23
Patent #:
Issue Dt:
11/14/2006
Application #:
10883237
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
DIELECTRIC STORAGE MEMORY CELL HAVING HIGH PERMITTIVITY TOP DIELECTRIC AND METHOD THEREFOR
24
Patent #:
Issue Dt:
01/27/2009
Application #:
10886340
Filing Dt:
07/07/2004
Publication #:
Pub Dt:
01/12/2006
Title:
MEMORY HAVING VARIABLE REFRESH CONTROL AND METHOD THEREFOR
25
Patent #:
Issue Dt:
06/15/2010
Application #:
10887132
Filing Dt:
07/08/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHOD AND SYSTEM FOR PERFORMING DEBLOCKING FILTERING
26
Patent #:
Issue Dt:
04/03/2007
Application #:
10889159
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
01/12/2006
Title:
MEMORY ROW/COLUMN REPLACEMENT IN AN INTEGRATED CIRCUIT
27
Patent #:
Issue Dt:
09/05/2006
Application #:
10891648
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD OF ASSEMBLING A SEMICONDUCTOR COMPONENT AND APPARATUS THEREFOR
28
Patent #:
Issue Dt:
10/28/2008
Application #:
10891649
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
02/23/2006
Title:
MEMORY WITH FAULT TOLERANT REFERENCE CIRCUITRY
29
Patent #:
Issue Dt:
09/11/2007
Application #:
10891811
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
01/19/2006
Title:
VOLTAGE REGULATOR WITH ADAPTIVE FREQUENCY COMPENSATION
30
Patent #:
Issue Dt:
06/06/2006
Application #:
10892420
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
01/19/2006
Title:
POWER ON RESET CIRCUIT
31
Patent #:
Issue Dt:
01/31/2006
Application #:
10892693
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
04/14/2005
Title:
DEVICE INCLUDING AN AMORPHOUS CARBON LAYER FOR IMPROVED ADHESION OF ORGANIC LAYERS AND METHOD OF FABRICATION
32
Patent #:
Issue Dt:
11/28/2006
Application #:
10893034
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
AUTOMATIC GAIN CONTROL FOR AN ADAPTIVE FINITE IMPULSE RESPONSE AND METHOD THEREFORE
33
Patent #:
Issue Dt:
09/12/2006
Application #:
10895552
Filing Dt:
07/21/2004
Publication #:
Pub Dt:
05/12/2005
Title:
HIGH K DIELECTRIC FILM
34
Patent #:
Issue Dt:
02/20/2007
Application #:
10895553
Filing Dt:
07/21/2004
Publication #:
Pub Dt:
01/26/2006
Title:
SEMICONDUCTOR DEVICE WITH LOW RESISTANCE CONTACTS
35
Patent #:
Issue Dt:
11/07/2006
Application #:
10901589
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/02/2006
Title:
METHOD FOR PREPARING A SEMICONDUCTOR SUBSTRATE SURFACE FOR SEMICONDUCTOR DEVICE FABRICATION
36
Patent #:
Issue Dt:
05/08/2007
Application #:
10901844
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/02/2006
Title:
SOLDERABLE METAL FINISH FOR INTEGRATED CIRCUIT PACKAGE LEADS AND METHOD FOR FORMING
37
Patent #:
Issue Dt:
05/29/2007
Application #:
10902021
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
SYSTEM AND METHOD FOR THE MITIGATION OF SPECTRAL LINES IN AN ULTRAWIDE BANDWIDTH TRANSCEIVER
38
Patent #:
Issue Dt:
01/16/2007
Application #:
10902204
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/02/2006
Title:
DYNAMIC LATCH HAVING INTEGRAL LOGIC FUNCTION AND METHOD THEREFOR
39
Patent #:
Issue Dt:
12/05/2006
Application #:
10902218
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/02/2006
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF
40
Patent #:
Issue Dt:
10/10/2006
Application #:
10903784
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURE HAVING ION IMPLANT IN ONLY ONE OF THE COMPLEMENTARY DEVICES
41
Patent #:
Issue Dt:
01/22/2008
Application #:
10903841
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
INTERFACIAL LAYER FOR USE WITH HIGH K DIELECTRIC MATERIALS
42
Patent #:
Issue Dt:
04/24/2007
Application #:
10909124
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/03/2005
Title:
SEMICONDUCTOR DEVICE WITH STRAIN RELIEVING BUMP DESIGN
43
Patent #:
Issue Dt:
01/30/2007
Application #:
10910036
Filing Dt:
08/03/2004
Publication #:
Pub Dt:
01/20/2005
Title:
METHOD FOR FORMING A BOND PAD INTERFACE
44
Patent #:
Issue Dt:
09/12/2006
Application #:
10911624
Filing Dt:
08/05/2004
Publication #:
Pub Dt:
03/17/2005
Title:
HETEROJUNCTION TUNNELING DIODES AND PROCESS FOR FABRICATING SAME
45
Patent #:
Issue Dt:
05/09/2006
Application #:
10912824
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
02/09/2006
Title:
MEMORY BIT LINE SEGMENT ISOLATION
46
Patent #:
Issue Dt:
01/09/2007
Application #:
10912825
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
02/09/2006
Title:
METHOD OF DISCHARGING A SEMICONDUCTOR DEVICE
47
Patent #:
Issue Dt:
06/05/2007
Application #:
10914006
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
02/09/2006
Title:
TUNGSTEN COATED SILICON FINGERS
48
Patent #:
Issue Dt:
07/24/2007
Application #:
10916298
Filing Dt:
08/11/2004
Publication #:
Pub Dt:
02/16/2006
Title:
PREFETCHING IN A DATA PROCESSING SYSTEM
49
Patent #:
Issue Dt:
12/04/2007
Application #:
10918457
Filing Dt:
08/16/2004
Publication #:
Pub Dt:
02/16/2006
Title:
METHOD FOR PROVIDING RAPID DELAYED FRAME ACKNOWLEDGEMENT IN A WIRELESS TRANSCEIVER
50
Patent #:
Issue Dt:
06/06/2006
Application #:
10919784
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
03/31/2005
Title:
SEMICONDUCTOR LAYER FORMATION
51
Patent #:
Issue Dt:
04/24/2007
Application #:
10919922
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
03/31/2005
Title:
TEMPLATE LAYER FORMATION
52
Patent #:
Issue Dt:
07/10/2007
Application #:
10919952
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
02/23/2006
Title:
GRADED SEMICONDUCTOR LAYER
53
Patent #:
Issue Dt:
12/27/2005
Application #:
10924632
Filing Dt:
08/24/2004
Title:
SEMICONDUCTOR TRANSISTOR HAVING STRUCTURAL ELEMENTS OF DIFFERING MATERIALS AND METHOD OF FORMATION
54
Patent #:
Issue Dt:
01/23/2007
Application #:
10924650
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD AND APPARATUS FOR PERFORMANCE ENHANCEMENT IN AN ASYMMETRICAL SEMICONDUCTOR DEVICE
55
Patent #:
Issue Dt:
01/09/2007
Application #:
10925084
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
03/02/2006
Title:
TRANSISTOR STRUCTURE WITH STRESS MODIFICATION AND CAPACITIVE REDUCTION FEATURE IN A WIDTH DIRECTION AND METHOD THEREOF
56
Patent #:
Issue Dt:
10/30/2007
Application #:
10925108
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD AND APPARATUS FOR MOBILITY ENHANCEMENT IN A SEMICONDUCTOR DEVICE
57
Patent #:
Issue Dt:
06/12/2007
Application #:
10925855
Filing Dt:
08/25/2004
Publication #:
Pub Dt:
03/02/2006
Title:
RECESSED SEMICONDUCTOR DEVICE
58
Patent #:
Issue Dt:
08/22/2006
Application #:
10926121
Filing Dt:
08/25/2004
Publication #:
Pub Dt:
03/02/2006
Title:
VARIABLE IMPEDANCE OUTPUT BUFFER
59
Patent #:
Issue Dt:
11/14/2006
Application #:
10927921
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
APPLICATIONS OF A HIGH IMPEDANCE SURFACE
60
Patent #:
Issue Dt:
11/14/2006
Application #:
10927944
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
FREQUENCY SELECTIVE HIGH IMPEDANCE SURFACE
61
Patent #:
Issue Dt:
02/27/2007
Application #:
10928399
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
DATA PROCESSING SYSTEM HAVING TRANSLATION LOOKASIDE BUFFER VALID BITS WITH LOCK AND METHOD THEREFOR
62
Patent #:
Issue Dt:
06/06/2006
Application #:
10930660
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
03/02/2006
Title:
MULTILAYER CAVITY SLOT ANTENNA
63
Patent #:
Issue Dt:
09/12/2006
Application #:
10930891
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
03/02/2006
Title:
PROGRAMMING AND ERASING STRUCTURE FOR AN NVM CELL
64
Patent #:
Issue Dt:
10/02/2012
Application #:
10933191
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD AND APPARATUS FOR MODIFYING AN INFORMATION UNIT USING AN ATOMIC OPERATION
65
Patent #:
Issue Dt:
07/03/2007
Application #:
10939148
Filing Dt:
09/10/2004
Publication #:
Pub Dt:
03/16/2006
Title:
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE SPACERS IN SIDEWALL REGIONS AND METHOD FOR FORMING
66
Patent #:
Issue Dt:
12/05/2006
Application #:
10940058
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/16/2006
Title:
OPEN LOOP MOTOR PARKING METHOD AND SYSTEM
67
Patent #:
Issue Dt:
11/11/2014
Application #:
10940121
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/16/2006
Title:
System and method for fetching information in response to hazard indication information
68
Patent #:
Issue Dt:
07/24/2007
Application #:
10940252
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/30/2006
Title:
METHOD AND APPARATUS FOR NON-INTRUSIVE TRACING
69
Patent #:
Issue Dt:
04/24/2007
Application #:
10943383
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL LAYER
70
Patent #:
Issue Dt:
05/02/2006
Application #:
10943579
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
MRAM SENSE AMPLIFIER HAVING A PRECHARGE CIRCUIT AND METHOD FOR SENSING
71
Patent #:
Issue Dt:
08/22/2006
Application #:
10944239
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING
72
Patent #:
Issue Dt:
02/27/2007
Application #:
10944244
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING
73
Patent #:
Issue Dt:
06/26/2007
Application #:
10944306
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
03/23/2006
Title:
SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER
74
Patent #:
Issue Dt:
10/09/2007
Application #:
10945319
Filing Dt:
09/20/2004
Publication #:
Pub Dt:
03/23/2006
Title:
DEPOSITION AND PATTERNING OF BORON NITRIDE NANOTUBE ILD
75
Patent #:
Issue Dt:
02/13/2007
Application #:
10946675
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
02/17/2005
Title:
SEMICONDUCTOR DEVICE HAVING A MULTIPLE THICKNESS INTERCONNECT
76
Patent #:
Issue Dt:
07/26/2005
Application #:
10946758
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
02/24/2005
Title:
SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES INCLUDING A VIA WITH AN END FORMED AT A BOTTOM SURFACE OF THE DIFFUSION REGION
77
Patent #:
Issue Dt:
07/04/2006
Application #:
10946938
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
03/23/2006
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A DIELECTRIC LAYER WITH HIGH DIELECTRIC CONSTANT
78
Patent #:
Issue Dt:
03/06/2007
Application #:
10946951
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
03/23/2006
Title:
METHOD AND APPARATUS FOR PROTECTING AN INTEGRATED CIRCUIT FROM ERRONEOUS OPERATION
79
Patent #:
Issue Dt:
04/08/2008
Application #:
10949057
Filing Dt:
09/23/2004
Publication #:
Pub Dt:
03/23/2006
Title:
SEMICONDUCTOR PROCESS WITH FIRST TRANSISTOR TYPES ORIENTED IN A FIRST PLANE AND SECOND TRANSISTOR TYPES ORIENTED IN A SECOND PLANE
80
Patent #:
Issue Dt:
11/29/2005
Application #:
10950855
Filing Dt:
09/27/2004
Publication #:
Pub Dt:
02/24/2005
Title:
NON-VOLATILE MEMORY HAVING A REFERENCE TRANSISTOR
81
Patent #:
Issue Dt:
06/27/2006
Application #:
10952676
Filing Dt:
09/29/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DOUBLE GATE DEVICE HAVING A HETEROJUNCTION SOURCE/DRAIN AND STRAINED CHANNEL
82
Patent #:
Issue Dt:
04/01/2008
Application #:
10952813
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
SYSTEM AND METHOD FOR ULTRA WIDEBAND COMMUNICATIONS USING MULTIPLE CODE WORDS
83
Patent #:
Issue Dt:
03/28/2006
Application #:
10954121
Filing Dt:
09/29/2004
Publication #:
Pub Dt:
03/30/2006
Title:
METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN
84
Patent #:
Issue Dt:
07/11/2006
Application #:
10954400
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/06/2006
Title:
PLASMA ENHANCED NITRIDE LAYER
85
Patent #:
Issue Dt:
10/21/2008
Application #:
10954793
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/06/2006
Title:
APPARATUS AND METHOD FOR HIGH SPEED VOLTAGE REGULATION
86
Patent #:
Issue Dt:
10/31/2006
Application #:
10954809
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DATA PROCESSING SYSTEM WITH BUS ACCESS RETRACTION
87
Patent #:
Issue Dt:
06/05/2007
Application #:
10955219
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DEVICE AND A METHOD FOR BIASING A TRANSISTOR THAT IS CONNECTED TO A POWER CONVERTER
88
Patent #:
Issue Dt:
10/07/2008
Application #:
10955220
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
APPARATUS AND METHOD FOR PROVIDING INFORMATION TO A CACHE MODULE USING FETCH BURSTS
89
Patent #:
Issue Dt:
04/22/2008
Application #:
10955356
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/20/2006
Title:
INTEGRATED CIRCUIT FUSES HAVING CORRESPONDING STORAGE CIRCUITRY
90
Patent #:
Issue Dt:
03/04/2008
Application #:
10955558
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
DATA PROCESSING SYSTEM WITH BUS ACCESS RETRACTION
91
Patent #:
Issue Dt:
11/14/2006
Application #:
10955658
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
ISOLATION TRENCH PERIMETER IMPLANT FOR THRESHOLD VOLTAGE CONTROL
92
Patent #:
Issue Dt:
09/19/2006
Application #:
10958831
Filing Dt:
10/05/2004
Publication #:
Pub Dt:
04/06/2006
Title:
WELL BIAS VOLTAGE GENERATOR
93
Patent #:
Issue Dt:
06/20/2006
Application #:
10961014
Filing Dt:
10/08/2004
Publication #:
Pub Dt:
04/13/2006
Title:
METHOD FOR FORMING A MULTI-BIT NON-VOLATILE MEMORY DEVICE
94
Patent #:
Issue Dt:
04/14/2009
Application #:
10961295
Filing Dt:
10/08/2004
Publication #:
Pub Dt:
04/13/2006
Title:
VIRTUAL GROUND MEMORY ARRAY AND METHOD THEREFOR
95
Patent #:
Issue Dt:
10/24/2006
Application #:
10962944
Filing Dt:
10/12/2004
Publication #:
Pub Dt:
04/13/2006
Title:
INTEGRATION OF MULTIPLE GATE DIELECTRICS BY SURFACE PROTECTION
96
Patent #:
Issue Dt:
08/01/2006
Application #:
10964793
Filing Dt:
10/14/2004
Publication #:
Pub Dt:
04/20/2006
Title:
BAND-GAP REFERENCE CIRCUIT
97
Patent #:
Issue Dt:
06/27/2006
Application #:
10965596
Filing Dt:
10/14/2004
Publication #:
Pub Dt:
03/03/2005
Title:
SYSTEM AND METHOD FOR CACHE EXTERNAL WRITING AND WRITE SHADOWING
98
Patent #:
Issue Dt:
05/02/2006
Application #:
10965964
Filing Dt:
10/15/2004
Publication #:
Pub Dt:
04/20/2006
Title:
LOW RC PRODUCT TRANSISTORS IN SOI SEMICONDUCTOR PROCESS
99
Patent #:
Issue Dt:
05/22/2007
Application #:
10967563
Filing Dt:
10/18/2004
Publication #:
Pub Dt:
04/20/2006
Title:
LOGIC CIRCUITRY
100
Patent #:
Issue Dt:
10/03/2006
Application #:
10967898
Filing Dt:
10/18/2004
Publication #:
Pub Dt:
04/20/2006
Title:
CIRCUIT AND METHOD FOR INTERPOLATIVE DELAY
Assignor
1
Exec Dt:
11/01/2013
Assignee
1
390 GREENWICH STREET
NEW YORK, NEW YORK 10013
Correspondence name and address
IP RESEARCH PLUS, INC.
21 TADCASTER CIRCLE
ATTN: PENELOPE J.A. AGODOA
WALDORF, MD 20602

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