Patent Assignment Details
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Reel/Frame: | 006597/0270 | |
| Pages: | 4 |
| | Recorded: | 06/17/1993 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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08/12/1997
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Application #:
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08078726
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Filing Dt:
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06/17/1993
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Title:
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SIGNAL PROCESSOR WITH DELAY LINE MANAGEMENT LOGIC
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Assignee
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15-12 SHIMOTAKAIDO, 1-CHOME |
SUGINAMI-KU, TOKYO, JAPAN |
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Correspondence name and address
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MARK A. HAYNES
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FLIESLER, DUBB, MEYER & LOVEJOY
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FOUR EMBARCADERO CENTER, SUITE 400
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SAN FRANCISCO, CA 94111
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