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Patent Assignment Details

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Reel/Frame:	019116/0277			Pages:	12
		Recorded:	03/29/2007
Conveyance:	CORRECTION TO CHANGE NATURE OF CONVEYANCE ON DOCUMENT #103361115 WITH R/F 018777/0202, CONVEYANCE SHOULD READ SECURITY AGREEMENT.

Total properties: 10

Patent #:	7139985	Issue Dt:	11/21/2006	Application #:	10871311	Filing Dt:	06/18/2004
Publication #:	US20050055657	Pub Dt:	03/10/2005
Title:	DEVELOPMENT SYSTEM FOR AN INTEGRATED CIRCUIT HAVING STANDARDIZED HARDWARE OBJECTS

Patent #:	7206870	Issue Dt:	04/17/2007	Application #:	10871347	Filing Dt:	06/18/2004
Publication #:	US20050005250	Pub Dt:	01/06/2005
Title:	DATA INTERFACE REGISTER STRUCTURE WITH REGISTERS FOR DATA, VALIDITY, GROUP MEMBERSHIP INDICATOR, AND READY TO ACCEPT NEXT MEMBER SIGNAL

Patent #:	7409533	Issue Dt:	08/05/2008	Application #:	11326701	Filing Dt:	01/06/2006
Publication #:	US20060117275	Pub Dt:	06/01/2006
Title:	ASYNCHRONOUS COMMUNICATION AMONG HARDWARE OBJECT NODES IN IC WITH RECEIVE AND SEND PORTS PROTOCOL REGISTERS USING TEMPORARY REGISTER BYPASS SELECT FOR VALIDITY INFORMATION

Patent #:	7801033	Issue Dt:	09/21/2010	Application #:	11340957	Filing Dt:	01/27/2006
Publication #:	US20070025382	Pub Dt:	02/01/2007
Title:	SYSTEM OF VIRTUAL DATA CHANNELS IN AN INTEGRATED CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	11458061	Filing Dt:	07/17/2006
Publication #:	US20070038782	Pub Dt:	02/15/2007
Title:	SYSTEM OF VIRTUAL DATA CHANNELS ACROSS CLOCK BOUNDARIES IN AN INTEGRATED CIRCUIT

Patent #:	7945803	Issue Dt:	05/17/2011	Application #:	11460231	Filing Dt:	07/26/2006
Publication #:	US20070064852	Pub Dt:	03/22/2007
Title:	CLOCK GENERATION FOR MULTIPLE CLOCK DOMAINS

Patent #:	7406584	Issue Dt:	07/29/2008	Application #:	11466083	Filing Dt:	08/21/2006
Publication #:	US20060282812	Pub Dt:	12/14/2006
Title:	IC COMPRISING NETWORK OF MICROPROCESSORS COMMUNICATING DATA MESSAGES ALONG ASYNCHRONOUS CHANNEL SEGMENTS USING PORTS INCLUDING VALIDITY AND ACCEPT SIGNAL REGISTERS AND WITH SPLIT/JOIN CAPABILITY

Patent #:	7673275	Issue Dt:	03/02/2010	Application #:	11466337	Filing Dt:	08/22/2006
Publication #:	US20060282813	Pub Dt:	12/14/2006
Title:	DEVELOPMENT SYSTEM FOR AN INTEGRATED CIRCUIT HAVING STANDARDIZED HARDWARE OBJECTS

Patent #:	NONE	Issue Dt:		Application #:	11557478	Filing Dt:	11/07/2006
Publication #:	US20070124565	Pub Dt:	05/31/2007
Title:	RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION NETWORK

Assignor

Exec Dt:

12/27/2006

Assignee

3003 TASMAN DRIVE

HF 154

SANTA CLARA, CALIFORNIA 95051

Correspondence name and address
	SILICON VALLEY BANK
	COLLATERAL HF154
	3003 TASMAN DRIVE
	SANTA CLARA, CA 95054

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