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Reel/Frame:	054340/0280			Pages:	12
		Recorded:	11/06/2020
Attorney Dkt #:	30100-10165549PT 1433601
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 63

Patent #:	8032660	Issue Dt:	10/04/2011	Application #:	12317896	Filing Dt:	12/30/2008
Publication #:	US20100169507	Pub Dt:	07/01/2010
Title:	APPARATUS AND METHOD FOR MANAGING SUBSCRIPTION REQUESTS FOR A NETWORK INTERFACE COMPONENT

Patent #:	8862973	Issue Dt:	10/14/2014	Application #:	12634286	Filing Dt:	12/09/2009
Publication #:	US20110138261	Pub Dt:	06/09/2011
Title:	METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE

Patent #:	8533538	Issue Dt:	09/10/2013	Application #:	12824675	Filing Dt:	06/28/2010
Publication #:	US20110320867	Pub Dt:	12/29/2011
Title:	METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGNAL OF A MEMORY

Patent #:	9251874	Issue Dt:	02/02/2016	Application #:	12974057	Filing Dt:	12/21/2010
Publication #:	US20120159059	Pub Dt:	06/21/2012
Title:	MEMORY INTERFACE SIGNAL REDUCTION

Patent #:	8943343	Issue Dt:	01/27/2015	Application #:	13528444	Filing Dt:	06/20/2012
Publication #:	US20130346771	Pub Dt:	12/26/2013
Title:	Controlling An Asymmetrical Processor

Patent #:	9012284	Issue Dt:	04/21/2015	Application #:	13560531	Filing Dt:	07/27/2012
Publication #:	US20130161756	Pub Dt:	06/27/2013
Title:	NANOWIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES

Patent #:	9158616	Issue Dt:	10/13/2015	Application #:	13619452	Filing Dt:	09/14/2012
Publication #:	US20130117641	Pub Dt:	05/09/2013
Title:	METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE

Patent #:	9164573	Issue Dt:	10/20/2015	Application #:	13785115	Filing Dt:	03/05/2013
Publication #:	US20130346778	Pub Dt:	12/26/2013
Title:	CONTROLLING AN ASYMMETRICAL PROCESSOR

Patent #:	9856136	Issue Dt:	01/02/2018	Application #:	13910133	Filing Dt:	06/05/2013
Publication #:	US20140361387	Pub Dt:	12/11/2014
Title:	CHIP ARRANGEMENT AND METHOD FOR MANUFACTURING A CHIP ARRANGEMENT

Patent #:	9495001	Issue Dt:	11/15/2016	Application #:	13972569	Filing Dt:	08/21/2013
Publication #:	US20150058650	Pub Dt:	02/26/2015
Title:	Forcing Core Low Power States In A Processor

Patent #:	9177867	Issue Dt:	11/03/2015	Application #:	13993330	Filing Dt:	07/29/2014
Publication #:	US20150041926	Pub Dt:	02/12/2015
Title:	TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS

Patent #:	9224808	Issue Dt:	12/29/2015	Application #:	13995913	Filing Dt:	06/19/2013
Publication #:	US20140131660	Pub Dt:	05/15/2014
Title:	UNIAXIALLY STRAINED NANOWIRE STRUCTURE

Patent #:	9224810	Issue Dt:	12/29/2015	Application #:	13996503	Filing Dt:	06/20/2013
Publication #:	US20140197377	Pub Dt:	07/17/2014
Title:	CMOS NANOWIRE STRUCTURE

Patent #:	9825130	Issue Dt:	11/21/2017	Application #:	13996845	Filing Dt:	01/24/2014
Publication #:	US20140264253	Pub Dt:	09/18/2014
Title:	LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS

Patent #:	9064944	Issue Dt:	06/23/2015	Application #:	13996848	Filing Dt:	06/21/2013
Publication #:	US20140264280	Pub Dt:	09/18/2014
Title:	NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS

Patent #:	10121861	Issue Dt:	11/06/2018	Application #:	13996850	Filing Dt:	06/21/2013
Publication #:	US20150129830	Pub Dt:	05/14/2015
Title:	NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS

Patent #:	8987794	Issue Dt:	03/24/2015	Application #:	13997118	Filing Dt:	06/21/2013
Publication #:	US20140225065	Pub Dt:	08/14/2014
Title:	NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF

Patent #:	9590089	Issue Dt:	03/07/2017	Application #:	13997162	Filing Dt:	06/21/2013
Publication #:	US20130341704	Pub Dt:	12/26/2013
Title:	VARIABLE GATE WIDTH FOR GATE ALL-AROUND TRANSISTORS

Patent #:	9552039	Issue Dt:	01/24/2017	Application #:	14125497	Filing Dt:	12/11/2013
Publication #:	US20140115368	Pub Dt:	04/24/2014
Title:	CONSTRAINED BOOT TECHNIQUES IN MULTI-CORE PLATFORMS

Patent #:	9449671	Issue Dt:	09/20/2016	Application #:	14132987	Filing Dt:	12/18/2013
Publication #:	US20140281206	Pub Dt:	09/18/2014
Title:	Techniques for Probabilistic Dynamic Random Access Memory Row Repair

Patent #:	9269436	Issue Dt:	02/23/2016	Application #:	14133011	Filing Dt:	12/18/2013
Publication #:	US20140281207	Pub Dt:	09/18/2014
Title:	TECHNIQUES FOR DETERMINING VICTIM ROW ADDRESSES IN A VOLATILE MEMORY

Patent #:	9129829	Issue Dt:	09/08/2015	Application #:	14274592	Filing Dt:	05/09/2014
Publication #:	US20140326952	Pub Dt:	11/06/2014
Title:	SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES

Patent #:	9716579	Issue Dt:	07/25/2017	Application #:	14581989	Filing Dt:	12/23/2014
Publication #:	US20160057754	Pub Dt:	02/25/2016
Title:	SUBCARRIER ALLOCATIONS FOR OPERATION IN MIXED BANDWIDTH ENVIRONMENTS

Patent #:	9252275	Issue Dt:	02/02/2016	Application #:	14582131	Filing Dt:	12/23/2014
Publication #:	US20150144880	Pub Dt:	05/28/2015
Title:	NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF

Patent #:	9385221	Issue Dt:	07/05/2016	Application #:	14688647	Filing Dt:	04/16/2015
Publication #:	US20150221744	Pub Dt:	08/06/2015
Title:	NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS

Patent #:	9343559	Issue Dt:	05/17/2016	Application #:	14690615	Filing Dt:	04/20/2015
Publication #:	US20150228772	Pub Dt:	08/13/2015
Title:	NANOWIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES

Patent #:	9595581	Issue Dt:	03/14/2017	Application #:	14789856	Filing Dt:	07/01/2015
Publication #:	US20150303258	Pub Dt:	10/22/2015
Title:	SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES

Patent #:	9637810	Issue Dt:	05/02/2017	Application #:	14860336	Filing Dt:	09/21/2015
Publication #:	US20160035724	Pub Dt:	02/04/2016
Title:	TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS

Patent #:	9580776	Issue Dt:	02/28/2017	Application #:	14860341	Filing Dt:	09/21/2015
Publication #:	US20160035725	Pub Dt:	02/04/2016
Title:	TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS

Patent #:	9728245	Issue Dt:	08/08/2017	Application #:	14865754	Filing Dt:	09/25/2015
Publication #:	US20160254044	Pub Dt:	09/01/2016
Title:	PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE

Patent #:	9761713	Issue Dt:	09/12/2017	Application #:	14941291	Filing Dt:	11/13/2015
Publication #:	US20160155843	Pub Dt:	06/02/2016
Title:	MULTI-THRESHOLD VOLTAGE DEVICES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Patent #:	10418487	Issue Dt:	09/17/2019	Application #:	14946744	Filing Dt:	11/19/2015
Publication #:	US20160079422	Pub Dt:	03/17/2016
Title:	NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF

Patent #:	9490320	Issue Dt:	11/08/2016	Application #:	14948039	Filing Dt:	11/20/2015
Publication #:	US20160079360	Pub Dt:	03/17/2016
Title:	UNIAXIALLY STRAINED NANOWIRE STRUCTURE

Patent #:	9583491	Issue Dt:	02/28/2017	Application #:	14948083	Filing Dt:	11/20/2015
Publication #:	US20160086951	Pub Dt:	03/24/2016
Title:	CMOS NANOWIRE STRUCTURE

Patent #:	9772799	Issue Dt:	09/26/2017	Application #:	14981307	Filing Dt:	12/28/2015
Publication #:	US20160188258	Pub Dt:	06/30/2016
Title:	MEMORY INTERFACE SIGNAL REDUCTION

Patent #:	9824754	Issue Dt:	11/21/2017	Application #:	15000643	Filing Dt:	01/19/2016
Publication #:	US20160224262	Pub Dt:	08/04/2016
Title:	Techniques for Determining Victim Row Addresses in a Volatile Memory

Patent #:	9812524	Issue Dt:	11/07/2017	Application #:	15155806	Filing Dt:	05/16/2016
Publication #:	US20160260802	Pub Dt:	09/08/2016
Title:	NANOWIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES

Patent #:	9614060	Issue Dt:	04/04/2017	Application #:	15173890	Filing Dt:	06/06/2016
Publication #:	US20160284821	Pub Dt:	09/29/2016
Title:	NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS

Patent #:	9953694	Issue Dt:	04/24/2018	Application #:	15174946	Filing Dt:	06/06/2016
Publication #:	US20170352406	Pub Dt:	12/07/2017
Title:	MEMORY CONTROLLER-CONTROLLED REFRESH ABORT

Patent #:	10659764	Issue Dt:	05/19/2020	Application #:	15187738	Filing Dt:	06/20/2016
Publication #:	US20170366801	Pub Dt:	12/21/2017
Title:	DEPTH IMAGE PROVISION APPARATUS AND METHOD

Patent #:	10609359	Issue Dt:	03/31/2020	Application #:	15190031	Filing Dt:	06/22/2016
Publication #:	US20170374352	Pub Dt:	12/28/2017
Title:	DEPTH IMAGE PROVISION APPARATUS AND METHOD

Patent #:	10199084	Issue Dt:	02/05/2019	Application #:	15197424	Filing Dt:	06/29/2016
Publication #:	US20170278562	Pub Dt:	09/28/2017
Title:	Techniques to Use Chip Select Signals for a Dual In-Line Memory Module

Patent #:	10102886	Issue Dt:	10/16/2018	Application #:	15269657	Filing Dt:	09/19/2016
Publication #:	US20170103795	Pub Dt:	04/13/2017
Title:	Techniques for Probabilistic Dynamic Random Access Memory Row Repair

Patent #:	9804793	Issue Dt:	10/31/2017	Application #:	15277182	Filing Dt:	09/27/2016
Publication #:	US20170255406	Pub Dt:	09/07/2017
Title:	Techniques for a Write Zero Operation

Patent #:	10310588	Issue Dt:	06/04/2019	Application #:	15296096	Filing Dt:	10/18/2016
Publication #:	US20170102752	Pub Dt:	04/13/2017
Title:	Forcing Core Low Power States In A Processor

Patent #:	9859368	Issue Dt:	01/02/2018	Application #:	15333123	Filing Dt:	10/24/2016
Publication #:	US20170047400	Pub Dt:	02/16/2017
Title:	INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

Patent #:	9905650	Issue Dt:	02/27/2018	Application #:	15339620	Filing Dt:	10/31/2016
Publication #:	US20170047405	Pub Dt:	02/16/2017
Title:	UNIAXIALLY STRAINED NANOWIRE STRUCTURE

Patent #:	10573747	Issue Dt:	02/25/2020	Application #:	15377994	Filing Dt:	12/13/2016
Publication #:	US20170092542	Pub Dt:	03/30/2017
Title:	MULTI-THRESHOLD VOLTAGE DEVICES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Patent #:	10490239	Issue Dt:	11/26/2019	Application #:	15391684	Filing Dt:	12/27/2016
Publication #:	US20180181344	Pub Dt:	06/28/2018
Title:	PROGRAMMABLE DATA PATTERN FOR REPEATED WRITES TO MEMORY

Patent #:	10552643	Issue Dt:	02/04/2020	Application #:	15392912	Filing Dt:	12/28/2016
Publication #:	US20180181336	Pub Dt:	06/28/2018
Title:	FAST BOOT UP MEMORY CONTROLLER

Patent #:	9812546	Issue Dt:	11/07/2017	Application #:	15401965	Filing Dt:	01/09/2017
Publication #:	US20170117378	Pub Dt:	04/27/2017
Title:	TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS

Patent #:	10636871	Issue Dt:	04/28/2020	Application #:	15410649	Filing Dt:	01/19/2017
Publication #:	US20170133462	Pub Dt:	05/11/2017
Title:	SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES

Patent #:	10074573	Issue Dt:	09/11/2018	Application #:	15411095	Filing Dt:	01/20/2017
Publication #:	US20170133277	Pub Dt:	05/11/2017
Title:	CMOS NANOWIRE STRUCTURE

Patent #:	10038054	Issue Dt:	07/31/2018	Application #:	15429126	Filing Dt:	02/09/2017
Publication #:	US20170154960	Pub Dt:	06/01/2017
Title:	VARIABLE GATE WIDTH FOR GATE ALL-AROUND TRANSISTORS

Patent #:	10361834	Issue Dt:	07/23/2019	Application #:	15610131	Filing Dt:	05/31/2017
Publication #:	US20180006793	Pub Dt:	01/04/2018
Title:	SUBCARRIER ALLOCATIONS FOR OPERATION IN MIXED BANDWIDTH ENVIRONMENTS

Patent #:	10109340	Issue Dt:	10/23/2018	Application #:	15639725	Filing Dt:	06/30/2017
Publication #:	US20180025773	Pub Dt:	01/25/2018
Title:	PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE

Patent #:	10559119	Issue Dt:	02/11/2020	Application #:	15692856	Filing Dt:	08/31/2017
Publication #:	US20190066362	Pub Dt:	02/28/2019
Title:	METHOD AND APPARATUS FOR NATURAL HAND VISUALIZATION

Patent #:	10395722	Issue Dt:	08/27/2019	Application #:	15721052	Filing Dt:	09/29/2017
Publication #:	US20190103154	Pub Dt:	04/04/2019
Title:	READING FROM A MODE REGISTER HAVING DIFFERENT READ AND WRITE TIMING

Patent #:	10020375	Issue Dt:	07/10/2018	Application #:	15726609	Filing Dt:	10/06/2017
Publication #:	US20180047825	Pub Dt:	02/15/2018
Title:	TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS

Patent #:	10031684	Issue Dt:	07/24/2018	Application #:	15788679	Filing Dt:	10/19/2017
Publication #:	US20180136861	Pub Dt:	05/17/2018
Title:	TECHNIQUES FOR A WRITE ZERO OPERATION

Patent #:	10121856	Issue Dt:	11/06/2018	Application #:	15859226	Filing Dt:	12/29/2017
Publication #:	US20180122901	Pub Dt:	05/03/2018
Title:	INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

Patent #:	10283589	Issue Dt:	05/07/2019	Application #:	16153456	Filing Dt:	10/05/2018
Publication #:	US20190051725	Pub Dt:	02/14/2019
Title:	INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

Patent #:	10580860	Issue Dt:	03/03/2020	Application #:	16358613	Filing Dt:	03/19/2019
Publication #:	US20190214461	Pub Dt:	07/11/2019
Title:	INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

Assignor

INTEL CORPORATION

Exec Dt:

07/23/2020

Assignee

SONY CORPORATION

1-7-1 KONAN

MINATO-KU, TOKYO, JAPAN

Correspondence name and address
	DANIEL M. GURFINKEL
	DENNEMEYER & ASSOCIATES, LLC
	2 NORTH RIVERSIDE PLAZA, SUITE 1500
	CHICAGO, IL 60606

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